PDF K7I161884B Data sheet ( Hoja de datos )

Número de pieza	K7I161884B
Descripción	512Kx36 & 1Mx18 DDRII CIO b4 SRAM
Fabricantes	Samsung semiconductor
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No Preview Available ! K7I163684B K7I161884B 512Kx36 & 1Mx18 DDRII CIO b4 SRAM 18Mb DDRII SRAM Specification 165FBGA with Pb & Pb-Free (RoHS compliant) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or simi- lar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung Electronics reserves the right to change products or specification without notice. www.DataSheet4U.com - 1 - Rev. 5.0 July 2006 1 page K7I163684B K7I161884B 512Kx36 & 1Mx18 DDRII CIO b4 SRAM PIN CONFIGURATIONS(TOP VIEW) K7I161884B(1Mx18) 1 2 3 4 5 6 7 8 9 10 11 A CQ NC/SA* SA R/W BW1 K NC LD SA NC/SA* CQ B NC DQ9 NC SA NC K BW0 SA NC NC DQ8 C NC NC NC VSS SA SA0 SA1 VSS NC DQ7 NC D NC NC DQ10 VSS VSS VSS VSS VSS NC NC NC E NC NC DQ11 VDDQ VSS VSS VSS VDDQ NC NC DQ6 F NC DQ12 NC VDDQ VDD VSS VDD VDDQ NC NC DQ5 G NC NC DQ13 VDDQ VDD VSS VDD VDDQ NC NC NC H Doff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ J NC NC NC VDDQ VDD VSS VDD VDDQ NC DQ4 NC K NC NC DQ14 VDDQ VDD VSS VDD VDDQ NC NC DQ3 L NC DQ15 NC VDDQ VSS VSS VSS VDDQ NC NC DQ2 M NC NC NC VSS VSS VSS VSS VSS NC DQ1 NC N NC NC DQ16 VSS SA SA SA VSS NC NC NC P NC NC DQ17 SA SA C SA SA NC NC DQ0 R TDO TCK SA SA SA C SA SA SA TMS TDI Notes: 1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 10A for 36Mb, 2A for 72Mb. 2. BW0 controls write to DQ0:DQ8 and BW1 controls write to DQ9:DQ17. PIN NAME SYMBOL K, K C, C CQ, CQ Doff SA0,SA1 SA DQ0-17 PIN NUMBERS 6B, 6A 6P, 6R 11A, 1A 1H 6C,7C 3A,9A,4B,8B,5C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R 2B,11B,10C,3D,3E,11E,2F,11F,3G,10J,3K,11K,2L,11L 10M,3N,3P,11P DESCRIPTION Input Clock Input Clock for Output Data Output Echo Clock DLL Disable when low Burst Count Address Inputs Address Inputs Data Inputs Outputs NOTE 1 R/W 4A Read, Write Control Pin, Read active when high LD 8A Synchronous Load Pin, bus Cycle sequence is to be defined when low BW0, BW1 7B, 5A Block Write Control Pin, active when low VREF 2H,10H Input Reference Voltage ZQ 11H Output Driver Impedance Control Input 2 VDD 5F,7F,5G,7G,5H,7H,5J,7J,5K,7K Power Supply ( 1.8 V ) VDDQ 4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L Output Power Supply ( 1.5V or 1.8V ) VSS 4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N Ground TMS 10R JTAG Test Mode Select TDI 11R JTAG Test Data Input TCK 2R JTAG Test Clock TDO 1R JTAG Test Data Output 2A,10A,7A,1B,3B,5B,9B,10B,1C,2C,3C,9C,11C,1D,2D,9D,10D, NC 11D,1E,2E,9E,10E,1F,3F,9F,10F,1G,2G,9G,10G,11G 1J,2J,3J,9J,11J,1K,2K,9K,10K,1L,3L,9L,10L No Connect 3 www.DataSheet4U.com 1M,2M,3M,9M,11M,1N,2N,9N,10N,11N,1P,2P,9P,10P Notes: 1. C, C, K or K cannot be set to VREF voltage. 2. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it cannot be connected to ground or left unconnected. 3. Not connected to chip pad internally. - 5 - Rev. 5.0 July 2006 5 Page K7I163684B K7I161884B 512Kx36 & 1Mx18 DDRII CIO b4 SRAM AC ELECTRICAL CHARACTERISTICS (VDD=1.8V ±0.1V, TA=0°C to +70°C) PARAMETER SYMBOL MIN MAX Input High Voltage VIH (AC) VREF + 0.2 - Input Low Voltage VIL (AC) - VREF - 0.2 Notes: 1. This condition is for AC function test only, not for AC parameter test. 2. To maintain a valid level, the transition edge of the input must: a) Sustain a constant slew rate from the current AC level through the target AC level, VIL(AC) or VIH(AC) b) Reach at least the target AC level c) After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC) Overershoot Timing Undershoot Timing UNIT V V NOTES 1,2 1,2 VDDQ+0.5V VDDQ+0.25V VDDQ 20% tKHKH(MIN) VIH VSS VSS-0.25V VSS-0.5V VIL Note: For power-up, VIH ≤ VDDQ+0.3V and VDD ≤ 1.7V and VDDQ ≤ 1.4V t ≤ 200ms OPERATING CONDITIONS (0°C ≤ TA ≤ 70°C) PARAMETER SYMBOL Supply Voltage VDD VDDQ Reference Voltage VREF Ground VSS MIN 1.7 1.4 0.68 0 20% tKHKH(MIN) MAX 1.9 1.9 0.95 0 UNIT V V V V AC TEST CONDITIONS Parameter Core Power Supply Voltage Output Power Supply Voltage Input High/Low Level Input Reference Level Input Rise/Fall Time Output Timing Reference Level Symbol VDD VDDQ VIH/VIL VREF TR/TF Note: Parameters are tested with RQ=250Ω Value 1.7~1.9 1.4~1.9 1.25/0.25 0.75 0.3/0.3 VDDQ/2 Unit V V V V ns V AC TEST OUTPUT LOAD VREF 0.75V VDDQ/2 SRAM Zo=50Ω 50Ω 250Ω ZQ www.DataSheet4U.com - 11 - Rev. 5.0 July 2006 11 Page

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