PDF K7B323625M Data sheet ( Hoja de datos )

Número de pieza	K7B323625M
Descripción	1Mx36 & 2Mx18 Synchronous SRAM
Fabricantes	Samsung semiconductor
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No Preview Available ! K7B323625M K7B321825M 1Mx36 & 2Mx18 Synchronous SRAM Document Title 1Mx36 & 2Mx18-Bit Synchronous Burst SRAM Revision History Rev. No. 0.0 History 1. Initial draft 0.1 1. Add 165FBGA package 0.2 1. Update JTAG scan order 0.3 1. Change pin out for 165FBGA - x18/x36 ; 11B => from A to NC , 2R ==> from NC to A . 0.4 1. Insert pin at JTAG scan order of 165FBGA in connection with pin out change - x18/x36 ; insert Pin ID of 2R to BIT number of 69 0.5 1. Add Icc, Isb, Isb1 and Isb2 values. 1.0 1. Correct the pin name of 100TQFP. 1.1 1. Change the Stand-by current (Isb) Before After Isb - 65 : 100 140 - 75 : 90 130 - 85 : 80 130 Isb1 : 90 110 Isb2 : 80 100 2.0 1. Delete the 119BGA and 165FBGA package. 2. Delete the 8.5ns speed bin Draft Date May. 10. 2001 Aug. 29. 2001 Dec. 03. 2001 Feb. 14 . 2002 Remark Advance Preliminary Preliminary Preliminary Apr. 20. 2002 Preliminary May. 10. 2002 Oct. 15. 2002 Oct. 17, 2003 Preliminary Final Final Nov. 18, 2003 Final www.DataSheet4U.com The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques- tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. - 1 - Nov. 2003 Rev 2.0 1 page K7B323625M K7B321825M PIN CONFIGURATION(TOP VIEW) 1Mx36 & 2Mx18 Synchronous SRAM N.C. N.C. N.C. VDDQ VSSQ N.C. N.C. D Q b0 D Q b1 VSSQ VDDQ D Q b2 D Q b3 N.C. VDD N.C. VSS D Q b4 D Q b5 VDDQ VSSQ D Q b6 D Q b7 DQPb N.C. VSSQ VDDQ N.C. N.C. N.C. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 Pin TQFP (20mm x 14mm) K7B321825M(2Mx18) 80 A10 79 N.C. 78 N.C. 77 VDDQ 76 VSSQ 75 N.C. 74 DQPa 73 DQa7 72 DQa6 71 VSSQ 70 VDDQ 69 DQa5 68 DQa4 67 VSS 66 N.C. 65 VDD 64 ZZ 63 DQa3 62 DQa2 61 VDDQ 60 VSSQ 59 DQa1 58 DQa0 57 N.C. 56 N.C. 55 VSSQ 54 VDDQ 53 N.C. 52 N.C. 51 N.C. PIN NAME SYMBOL PIN NAME TQFP PIN NO. SYMBOL PIN NAME TQFP PIN NO. A0 - A20 Address Inputs ADV Burst Address Advance ADSP Address Status Processor ADSC Address Status Controller CLK Clock CS1 Chip Select CS2 Chip Select CS2 Chip Select W Ex(x=a,b) Byte Write Inputs OE Output Enable G W Global Write Enable B W Byte Write Enable www.DaZtaZSheet4U.cPoowmer Down Input LBO Burst Mode Control 32,33,34,35,36,37,39 42,43,44,45,46,47,48, 49,50 80,81,82,99,100 83 84 85 89 98 97 92 93,94 86 88 87 64 31 VDD VSS N.C. DQa0 ~ a7 DQb0 ~ b7 DQPa, Pb VDDQ VSSQ Power Supply(+3.3V) Ground No Connect 15,41,65,91 17,40,67,90 1,2,3,6,7,14,16,25,28,29, 30,38,51,52,53,56,57,66, 75,78,79,95,96 Data Inputs/Outputs 58,59,62,63,68,69,72,73 8,9,12,13,18,19,22,23 74,24 Output Power Supply (2.5V or 3.3V) Output Ground 4,11,20,27,54,61,70,77 5,10,21,26,55,60,71,76 Notes : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. - 5 - Nov. 2003 Rev 2.0 5 Page K7B323625M K7B321825M 1Mx36 & 2Mx18 Synchronous SRAM www.DataSheet4U.com - 11 - Nov. 2003 Rev 2.0 11 Page

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