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KSZ8842-16MVIL 데이터시트 PDF




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부품번호 KSZ8842-16MVIL 기능
기능 2-Port Ethernet Switch
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KSZ8842-16MVIL 데이터시트, 핀배열, 회로
KSZ8842-16/32
MQL/MVL/MVLI/MBL
2-Port Ethernet Switch with Non-PCI Interface
Data Sheet Rev 1.9
General Description
The KSZ8842-series of 2-port switches includes PCI and
non-PCI CPU interfaces, and are available in 8/16-bit
and 32-bit bus designs (see Ordering Information).
This datasheet describes the KSZ8842M-series of non-
PCI CPU interface chips. For information on the
KSZ8842 PCI CPU interface switches, refer to the
KSZ8842P datasheet.
The KSZ8842M is the industry’s first fully managed, 2-
port switch with a non-PCI CPU interface. It is based on
a proven, 4th generation, integrated Layer-2 switch,
compliant with IEEE 802.3u standards. Also an industrial
temperature grade version of the KSZ8842, the
KSZ8842MVLI, can be ordered (see Ordering
Information).
The KSZ8842M can be configured as a switch or as a
low-latency (310 nanoseconds) repeater in latency-
critical, embedded or industrial Ethernet applications.
For industrial applications, the KSZ8842M can run in
half-duplex mode regardless of the application.
Functional Diagram
LinkMD®
The KSZ8842M offers an extensive feature set that
includes tag/port-based VLAN, quality of service (QoS)
priority management, management information base
(MIB) counters, and CPU control/data interfaces to
effectively address Fast Ethernet applications.
The KSZ8842M contains: Two 10/100 transceivers with
patented, mixed-signal, low-power technology, two
media access control (MAC) units, a direct memory
access (DMA) channel, a high-speed, non-blocking,
switch fabric, a dedicated 1K entry forwarding table, and
an on-chip frame buffer memory.
P 1 H P A u to
M D I/M D I-X
P 2 H P A u to
M D I/M D I-X
10 /10 0 B ase -
T /T X
PHY 1
10 /10 0 B ase -
T /T X
PHY 2
10 /1 00
MAC 1
10 /1 00
MAC 2
Em bedded
P ro ce ss o r In te rfa c e
N on-P C I
CPU
Bus
In te rfa c e
U nit
QMU
DMA
C hannel
8 ,1 6 , o r 3 2 -b it
G en eric H o st
In te rface
P 1 L E D [3 :0 ]
P 2 L E D [3 :0 ]
www.DataSheet4U.com
E E P R O M I/F
LED
D rive rs
RXQ
4KB
TXQ
4KB
C on trol
R e g is te rs
S w itc h
H ost
MAC
1 K lo o k -u p
E n g in e
S c h e d u lin g
M anagem ent
B uffe r
M anagem ent
F ram e
B u ffers
M IB
C ou nte rs
EEPROM
Inte rface
Figure 1. KSZ8842M Functional Diagram
LinkMD is a registered trademark of Micrel, Inc.
Product names used in this datasheet are for identification purposes only and may be trademarks of their respective companies
October 2007
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M9999-102207-1.9




KSZ8842-16MVIL pdf, 반도체, 판매, 대치품
Micrel, Inc.
KSZ8842-16/32 MQL/MVL/MVLI/MBL
Content
Pin Configuration for KSZ8842-16 Switches (8/16-Bit) ...................................................................................... 11
Ball Configuration for KSZ8842-16 Switches (8/16-Bit) ..................................................................................... 12
Pin Description for KSZ8842-16 Switches (8/16-Bit) .......................................................................................... 13
Ball Description for KSZ8842-16 Switches (8/16-Bit) ......................................................................................... 18
Pin Configuration for KSZ8842-32 Switches (32-Bit).......................................................................................... 22
Pin Description for KSZ8842-32 Switches (32-Bit) ............................................................................................. 23
Functional Description .......................................................................................................................................... 28
Functional Overview: Physical Layer Transceiver ............................................................................................. 28
100BASE-TX Transmit ..........................................................................................................................................................28
100BASE-TX Receive ...........................................................................................................................................................28
Scrambler/De-scrambler (100BASE-TX only)........................................................................................................................28
10BASE-T Transmit...............................................................................................................................................................28
10BASE-T Receive................................................................................................................................................................28
Power Management...............................................................................................................................................................29
MDI/MDI-X Auto Crossover ...................................................................................................................................................29
Straight Cable ...................................................................................................................................................................29
Crossover Cable ...............................................................................................................................................................30
Auto Negotiation ....................................................................................................................................................................30
LinkMD Cable Diagnostics.....................................................................................................................................................31
Access ..............................................................................................................................................................................31
Usage ...............................................................................................................................................................................32
Functional Overview: MAC and Switch ............................................................................................................... 32
Address Lookup.....................................................................................................................................................................32
Learning.................................................................................................................................................................................32
Migration ................................................................................................................................................................................32
Aging .....................................................................................................................................................................................32
Forwarding.............................................................................................................................................................................33
Switching Engine ...................................................................................................................................................................35
MAC Operation......................................................................................................................................................................35
Inter Packet Gap (IPG) ..........................................................................................................................................................35
Back-Off Algorithm.................................................................................................................................................................35
Late Collision .........................................................................................................................................................................35
Legal Packet Size..................................................................................................................................................................35
Flow Control ..........................................................................................................................................................................35
Half-Duplex Backpressure .....................................................................................................................................................35
Broadcast Storm Protection...................................................................................................................................................36
Repeater Mode......................................................................................................................................................................36
Clock Generator ....................................................................................................................................................................36
Bus Interface Unit (BIU)......................................................................................................................................... 36
Asynchronous Interface .........................................................................................................................................................38
Synchronous Interface...........................................................................................................................................................39
Summary ...............................................................................................................................................................................39
BIU Implementation Principles...............................................................................................................................................41
wwQwue.DuaetaMShaeneat4gUe.mcoemnt Unit (QMU) ........................................................................................................................... 41
Transmit Queue (TXQ) Frame Format...................................................................................................................................41
Receive Queue (RXQ) Frame Format ...................................................................................................................................42
Advanced Switch Functions ................................................................................................................................. 44
Spanning Tree Support..........................................................................................................................................................44
IGMP Support........................................................................................................................................................................45
“IGMP” Snooping ..............................................................................................................................................................45
October 2007
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KSZ8842-16MVIL 전자부품, 판매, 대치품
Micrel, Inc.
KSZ8842-16/32 MQL/MVL/MVLI/MBL
Bank 48 Port 1 VID Control Register (0x04): P1VIDCR.......................................................................................................101
Bank 48 Port 1 Control Register 3 (0x06): P1CR3 ..............................................................................................................101
Bank 48 Port 1 Ingress Rate Control Register (0x08): P1IRCR...........................................................................................102
Bank 48 Port 1 Egress Rate Control Register (0x0A): P1ERCR .........................................................................................104
Bank 49 Port 1 PHY Special Control/Status, LinkMD (0x00): P1SCSLMD..........................................................................106
Bank 49 Port 1 Control Register 4 (0x02): P1CR4 ..............................................................................................................107
Bank 49 Port 1 Status Register (0x04): P1SR .....................................................................................................................108
Bank 50 Port 2 Control Register 1 (0x00): P2CR1 ..............................................................................................................109
Bank 50 Port 2 Control Register 2 (0x02): P2CR2 ..............................................................................................................109
Bank 50 Port 2 VID Control Register (0x04): P2VIDCR.......................................................................................................109
Bank 50 Port 2 Control Register 3 (0x06): P2CR3 ..............................................................................................................109
Bank 50 Port 2 Ingress Rate Control Register (0x08): P2IRCR...........................................................................................109
Bank 50 Port 2 Egress Rate Control Register (0x0A): P2ERCR .........................................................................................109
Bank 51 Port 2 PHY Special Control/Status, LinkMD (0x00): P2SCSLMD..........................................................................110
Bank 51 Port 2 Control Register 4 (0x02): P2CR4 ..............................................................................................................111
Bank 51 Port 2 Status Register (0x04): P2SR .....................................................................................................................113
Bank 52 Host Port Control Register 1 (0x00): P3CR1 .........................................................................................................114
Bank 52 Host Port Control Register 2 (0x02): P3CR2 .........................................................................................................114
Bank 52 Host Port VID Control Register (0x04): P3VIDCR .................................................................................................115
Bank 52 Host Port Control Register 3 (0x06): P3CR3 .........................................................................................................115
Bank 52 Host Port Ingress Rate Control Register (0x08): P3IRCR .....................................................................................115
Bank 52 Host Port Egress Rate Control Register (0x0A): P3ERCR ....................................................................................115
Banks 53 – 63: Reserved ....................................................................................................................................................115
MIB (Management Information Base) Counters................................................................................................ 116
Format of “All Ports Dropped Packet” MIB Counters ...........................................................................................................117
Additional MIB Information...................................................................................................................................................118
Static MAC Address Table .................................................................................................................................. 119
Static MAC Table Lookup Examples: ..................................................................................................................................119
Dynamic MAC Address Table ............................................................................................................................. 120
Dynamic MAC Address Lookup Example: ...........................................................................................................................120
VLAN Table ........................................................................................................................................................... 121
VLAN Table Lookup Examples:...........................................................................................................................................121
Absolute Maximum Ratings(1) ............................................................................................................................. 122
Operating Ratings(1) ............................................................................................................................................. 122
Electrical Characteristics(1) ................................................................................................................................. 123
Timing Specifications .......................................................................................................................................... 124
Asynchronous Timing without using Address Strobe (ADSN = 0) .......................................................................................124
Asynchronous Timing using Address Strobe (ADSN)..........................................................................................................125
Asynchronous Timing using DATACSN (KSZ8842-32MQL/MVL device only) ....................................................................126
Address Latching Timing for All Modes ...............................................................................................................................127
Synchronous Timing in Burst Write (VLBUSN = 1)..............................................................................................................128
Synchronous Timing in Burst Read (VLBUSN = 1)..............................................................................................................129
Synchronous Write Timing (VLBUSN = 0)...........................................................................................................................130
Synchronous Read Timing (VLBUSN = 0)...........................................................................................................................131
EEPROM Timing .................................................................................................................................................................132
wwwA.DutaotaNSehgeoetti4aUtio.cnomTiming ......................................................................................................................................................133
Reset Timing .......................................................................................................................................................................134
Selection of Isolation Transformers................................................................................................................... 135
Selection of Reference Crystal ........................................................................................................................... 135
Package Information ............................................................................................................................................ 136
Acronyms and Glossary...................................................................................................................................... 139
October 2007
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KSZ8842-16MVIL

2-Port Ethernet Switch

Micrel Semiconductor
Micrel Semiconductor

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