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PDF KSZ8842-PMQL Data sheet ( Hoja de datos )
| Número de pieza | KSZ8842-PMQL | |
| Descripción | 2-Port Ethernet Switch | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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KSZ8842-PMQL/PMBL
2-Port Ethernet Switch with PCI Interface
Rev.1.5
General Description
The KSZ8842-series of 2-port switches includes PCI and
non-PCI CPU interfaces. This datasheet describes the
KSZ8842-PMQL/PMBL PCI CPU interface chips.
KSZ8842-PMQL is PQFP package chip, KSZ8842-PMBL
is LFBGA package chip. For information on the
KSZ8842-MQL/MBL CPU non-PCI interface switches,
refer to the KSZ8842-MQL/MBL datasheet.
The KSZ8842-PMQL/PMBL is the industry’s first fully
managed 2-port switch with a 32 bit/33MHz PCI
processor interface. It is a proven, 4th generation,
integrated Layer 2 switch that is compliant with the IEEE
802.3u standard. An industrial temperature grade version
of the KSZ8842-PMQL/PMBL, also can be ordered the
KSZ8842-PMQLI/PMBL AM.
The KSZ8842-PMQL/PMBL can be configured as a
switch or as a low-latency (<310 nanoseconds) repeater
in latency-critical, embedded or industrial Ethernet
applications. For industrial automation applications, the
LinkMD®
KSZ8842-PMQL/PMBL can run in half-duplex mode
regardless of the application. The KSZ8842-PMQL/PMBL
offers an extensive feature set that includes tag/port-
based VLAN, quality of service (QoS) priority
management, management information base (MIB)
counters, and CPU control/data interfaces to effectively
address Fast Ethernet applications.
The KSZ8842-PMQL/PMBL contains two 10/100
transceivers with patented, mixed-signal, low-power
technology three media access control (MAC) units, a
direct memory access (DMA) channel, a high-speed,
non-blocking, switch fabric, a dedicated 1K entry
forwarding table, and an on-chip frame buffer memory.
Datasheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
Functional Diagram
www.DataSheet4U.com
Figure 1. KSZ8842-PMQL/PMBL Functional Diagram
LinkMD is a registered trademark of Micrel, Inc
Magic Packet is a trademark of Advanced Micro Devices, Inc.
Product/Application names used in this datasheet are for identification purposes only and may be trademarks of their respective companies.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
October 2007
M9999-100207-1.5
1 page  
Micrel, Inc.
KSZ8842-PMQL/PMBL
Configuration Interface.................................................................................................................................................. 33
EEPROM Interface ....................................................................................................................................................... 33
Loop back Support........................................................................................................................................................ 33
Host Communication ...................................................................................................................................................... 35
Host Communication Descriptor Lists and Data Buffers .............................................................................................. 35
Receive Descriptors (RDES0-RDES3) ......................................................................................................................... 35
Transmit Descriptors (TDES0-TDES3)......................................................................................................................... 37
PCI Configuration Registers .......................................................................................................................................... 39
Configuration ID Register (CFID Offset 00H) ............................................................................................................... 39
Command and Status Configuration Register (CFCS Offset 04H)............................................................................... 39
Configuration Revision Register (CFRV Offset 08H).................................................................................................... 41
Configuration Latency Timer Register (CFLT Offset 0CH)........................................................................................... 41
Configuration Base Memory Address Register (CBMA Offset 10H) ............................................................................ 42
Subsystem ID Register (CSID Offset 2CH) .................................................................................................................. 42
Configuration Interrupt Register (CFIT Offset 3CH) ..................................................................................................... 42
PCI Control & Status Registers ..................................................................................................................................... 43
MAC DMA Transmit Control Register (MDTXC Offset 0x0000) ................................................................................... 43
MAC DMA Receive Control Register (MDRXC Offset 0x0004).................................................................................... 44
MAC DMA Transmit Start Command Register (MDTSC Offset 0x0008) ..................................................................... 45
MAC DMA Receive Start Command Register (MDRSC Offset 0x000C) ..................................................................... 46
Transmit Descriptor List Base Address Register (TDLB Offset 0x0010)...................................................................... 46
Receive Descriptor List Base Address Register (RDLB Offset 0x0014) ...................................................................... 46
Reserved (Offset 0x0018)............................................................................................................................................. 46
Reserved (Offset 0x001C) ............................................................................................................................................ 46
MAC Multicast Table 0 Register (MTR0 Offset 0x0020) .............................................................................................. 46
MAC Multicast Table 1 Register (MTR1 Offset 0x0024) .............................................................................................. 47
Interrupt Enable Register (INTEN Offset 0x0028) ........................................................................................................ 47
Interrupt Status Register (INTST Offset 0x002C) ......................................................................................................... 48
MAC Additional Station Address Low Register (MAAL0-15) ........................................................................................ 49
MAC Additional Station Address High Register (MAAH0-15)....................................................................................... 49
MAC/PHY and Control Registers ................................................................................................................................... 50
MAC Address Register Low (0x0200): MARL .............................................................................................................. 50
MAC Address Register Middle (0x0202): MARM ......................................................................................................... 50
MAC Address Register High (0x0204): MARH ............................................................................................................. 50
Reserved (Offset 0x0206 - 0x020A .............................................................................................................................. 51
On-Chip Bus Control Register (Offset 0x0210): OBCR................................................................................................ 51
EEPROM Control Register (Offset 0x0212): EEPCR................................................................................................... 51
Memory BIST Info Register (Offset 0x0214): MBIR ..................................................................................................... 52
Global Reset Register (Offset 0x0216): GRR............................................................................................................... 52
Switch Registers ............................................................................................................................................................. 52
Switch ID and Enable Register (Offset 0x0400): SIDER .............................................................................................. 52
Switch Global Control Register 1 (Offset 0x0402): SGCR1 ......................................................................................... 53
Switch Global Control Register 2 (Offset 0x0404): SGCR2 ......................................................................................... 54
Switch Global Control Register 3 (Offset 0x0406): SGCR3 ......................................................................................... 55
Switch Global Control Register 4 (Offset 0x0408): SGCR4 ......................................................................................... 56
Switch Global Control Register 5 (Offset 0x040A): SGCR5 ......................................................................................... 56
Switch Global Control Register 6 (Offset 0x0410): SGCR6 ......................................................................................... 57
Switch Global Control Register 7 (0x0412): SGCR7 .................................................................................................... 58
Reserved (Offset 0x0414 - 0x046F) ............................................................................................................................. 58
MAC Address Register 1 (Offset 0x0470): MACAR1 ................................................................................................... 58
www.DMatAaSCheAedt4dUre.csosmRegister 2 (Offset 0x0472): MACAR2 ................................................................................................... 58
MAC Address Register 3 (Offset 0x0474): MACAR3 ................................................................................................... 58
Reserved (Offset 0x0476 - 0x047F) ............................................................................................................................. 58
Priority Control Register 1 (Offset 0x0480): TOSR1..................................................................................................... 59
TOS Priority Control Register 2 (Offset 0x482): TOSR2 .............................................................................................. 59
TOS Priority Control Register 3 (Offset 0x484): TOSR3 .............................................................................................. 60
October 2007
5 M9999-100207-1.5
5 Page 
Micrel, Inc.
KSZ8842-PMQL/PMBL
Pins Description of KSZ8842-PMQL
Pin
Number
1
Pin
Name
TEST_EN
2 SCAN_EN
3 P1LED2
4 P1LED1
5 P1LED0
6 P2LED2
7 P2LED1
8 P2LED0
Type
Pin Function
I Test Enable
For normal operation, pull-down this pin to ground.
I Scan Test Scan Mux Enable
For normal operation, pull-down this pin to ground.
Opu Port 1 and Port 2 LED indicators1 defined as follows:
Opu LEDs turn on when low.
Opu
Opu
Opu
Opu P1LED32 /P2LED3
P1LED2/P2LED2
Chip Global Control Register 5:
SGCR5 bit [15,9]
[0,0] Default
[0,1]
——
Link/Act
100Link/Act
P1LED1/P2LED1
Full duplex/Col 10Link/Act
P1LED0/P2LED0
Speed
Full duplex
www.DataSheet4U.com
9 DGND
10 VDDIO
Reg. SGCR5 bit [15,9]
P1LED32 /P2LED3
[1,0]
Act
[1,1]
—
P1LED2/P2LED2
Link
—
P1LED1/P2LED1
Full duplex/Col —
P1LED0/P2LED0
Speed
—
Notes:
1. Link = On; Activity = Blink; Link/Act = On/Blink; Full Dup/Col = On/Blink;
Full Duplex = On (Full duplex); Off (Half duplex)
Speed = On (100BASE-T); Off (10BASE-T)
2. P1LED3 is pin 27. P2LED3 is pin 22
Port 1 and Port 2 LED indicators1 for Repeater mode defined as follows:
Switch Global Control Register 5:
SGCR5 bit [15,9]
[0,0] Default
[0,1] [1,0],[1,1]
P1LED3/P2LED3
RPT_COL,
RPT_ACT
—
P1LED2/P2LED2
RPT_Link3/RX,
RPT_ERR3
—
P1LED1/P2LED1
RPT_Link2/RX,
RPT_ERR2
—
P1LED0/P2LED0
RPT_Link1/RX,
RPT_ERR1
—
Note:
1. RPT_COL = Blink; RPT_Link3/RX (Host port) = On/Blink;
RPT_Link2/RX (Port 2) = On/Blink; RPT_Link1/RX (Port 1) = On/Blink;
RPT_ACT = On if any activity; RPT_ERR3 (Host port) = On if any CRC error;
RPT_ERR2 (port 2) = On if any CRC error; RPT_ERR1 (port 1) = On if any CRC error;
Gnd Digital ground
P 3.3V digital I/O VDD
October 2007
11 M9999-100207-1.5
11 Page | ||
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