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PDF FAN6300A Data sheet ( Hoja de datos )
| Número de pieza | FAN6300A | |
| Descripción | Highly Integrated Quasi-Resonant Current Mode PWM Controller | |
| Fabricantes | Fairchild Semiconductor | |
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December 2009
FAN6300A / FAN6300H
Highly Integrated Quasi-Resonant Current Mode
PWM Controller
Features
High-Voltage Startup
Quasi-Resonant Operation
Cycle-by-Cycle Current Limiting
Peak-Current-Mode Control
Leading-Edge Blanking (LEB)
Internal Minimum tOFF
Internal 5ms Soft-Start
Over Power Compensation
GATE Output Maximum Voltage
Auto-Recovery Over-Current Protection(FB Pin)
Auto-Recovery Open-Loop Protection(FB Pin)
VDD Pin and Output Voltage (DET Pin)
OVP Latched
Low Frequency Operation (below 100kHz) for
FAN6300A
High Frequency Operation (up to 190kHz) for
FAN6300H
Applications
AC/DC NB Adapters
Open-Frame SMPS
www.DataSheet4U.com
Description
The highly integrated FAN6300A/H of PWM controller
provides several features to enhance the performance
of flyback converters. FAN6300A is applied on quasi-
resonant flyback converters where maximum operating
frequency is below 100kHz. FAN6300H is suitable for
high-frequency operation (up to 190kHz). A built-in HV
startup circuit can provide more startup current to
reduce the startup time of the controller. Once the VDD
voltage exceeds the turn-on threshold voltage, the HV
startup function is disabled immediately to reduce
power consumption. An internal valley voltage detector
ensures power system operates at quasi-resonant
operation over a wide-range of line voltage and any
load conditions, as well as reducing switching loss to
minimize switching voltage on drain of power MOSFET.
To minimize standby power consumption and light-load
efficiency, a proprietary green-mode function provides
off-time modulation to decrease switching frequency
and perform extended valley voltage switching to keep
to a minimum switching voltage. The operating
frequency is limited by minimum toff time, which is 38µs
to 8µs in FAN6300A and 13µs to 3µs in FAN6300H, so
FAN6300H can operate at higher switching frequency
than FAN6300A.
FAN6300A/H controller also provides many protection
functions. Pulse-by-pulse current limiting ensures the
fixed-peak current limit level, even when a short circuit
occurs. Once an open-circuit failure occurs in the
feedback loop, the internal protection circuit disables
PWM output immediately. As long as VDD drops below
the turn-off threshold voltage, the controller also
disables PWM output. The gate output is clamped at
18V to protect the power MOS from high gate-source
voltage conditions. The minimum tOFF time limit
prevents the system frequency from being too high. If
the DET pin triggers OVP, internal OTP is triggered and
the power system enters latch-mode until AC power is
removed.
The FAN6300A/H controller is available in the 8-pin
Small Outline Package (SOP) and the Dual Inline
Package (DIP).
© 2009 Fairchild Semiconductor Corporation
FAN6300A/H • Rev. 1.0.1
www.fairchildsemi.com
1 page  
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Unit
VDD DC Supply Voltage
30 V
VHV HV
500 V
VH GATE
-0.3 25.0
V
VL VFB, VCS, VDET
-0.3 7.0
V
PD Power Dissipation
SOP-8
DIP-8
400
mW
800
TJ Operating Junction Temperature
+150
°C
TSTG Storage Temperature Range
-55 +150 °C
TL Lead Temperature (Soldering 10 Seconds)
+270
°C
ESD
Human Body Model, JEDEC:JESD22-A114
Charged Device Model, JEDEC:JESD22-C101
3.0
KV
1.5
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
2. All voltage values, except differential voltages, are given with respect to GND pin.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
TA Operating Ambient Temperature
Conditions
Min.
-40
Typ.
Max.
+125
Unit
°C
www.DataSheet4U.com
© 2009 Fairchild Semiconductor Corporation
FAN6300A / FAN6300H • Rev. 1.0.1
5
www.fairchildsemi.com
5 Page 
Operation Description
The FAN6300A/H PWM controller integrates designs to
enhance the performance of flyback converters. An
internal valley voltage detector ensures power system
operates at Quasi-Resonant (QR) operation across a
wide range of line voltage. The following descriptions
highlight some of the features of the FAN6300A/H.
Startup Current
For startup, the HV pin is connected to the line input or
bulk capacitor through an external diode and resistor,
RHV, which are recommended as 1N4007 and 100kΩ.
Typical startup current drawn from the HV pin is 1.2mA
and it charges the hold-up capacitor through the diode
and resistor. When the VDD voltage level reaches VDD-ON,
the startup current switches off. At this moment, the VDD
capacitor only supplies the FAN6300A/H to maintain VDD
until the auxiliary winding of the main transformer
provides the operating current.
Valley Detection
The DET pin is connected to an auxiliary winding of the
transformer via resistors of the divider to generate a
valley signal once the secondary-side switching current
discharges to zero. It detects the valley voltage of the
switching waveform to achieve the valley voltage
switching. This ensures QR operation, minimizes
switching losses, and reduces EMI. Figure 17 shows
divider resistors RDET and RA. RDET is recommended as
150kΩ to 220kΩ to achieve valley voltage switching.
When VAUX (in Figure 17) is negative, the DET pin
voltage is clamped to 0.3V.
Green-Mode Operation
The proprietary green-mode function provides off-time
modulation to linearly decrease the switching frequency
under light-load conditions. VFB, which is derived from
the voltage feedback loop, is taken as the reference. In
Figure 19, once VFB is lower than VN, tOFF-MIN increases
linearly with lower VFB. The valley voltage detection
signal does not start until tOFF-MIN finishes. Therefore, the
valley detect circuit is activated until tOFF-MIN finishes,
which decreases the switching frequency and provides
extended valley voltage switching. However, in very light
load condition, it might fail to detect the valley voltage
after the tOFF-MIN expires. Under this condition, an internal
tTIME-OUT signal initiates a new cycle start after a 9μs
delay (with 5µs delay for H version). Figure 20 and
Figure 21 show the two different conditions.
tO FF -M IN
2 .1 m s
38/13 μ s
8 /3μ s
1 .2 V
2 .1 V
Figure 19. VFB vs. tOFF-MIN Curve
VFB
Figure 17. Valley Detect Section
The internal timer (minimum tOFF time) prevents gate
retriggering within 8µs (3µs for H version) after the gate
signal going-low transition. The minimum tOFF limit
prevents system frequency being too high. Figure 18
shows a typical drain voltage waveform with first valley
switching.
Figure 20. QR Operation in Extended Valley Voltage
Detection Mode
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Figure 18. First Valley Switching
© 2009 Fairchild Semiconductor Corporation
FAN6300A / FAN6300H • Rev. 1.0.1
Figure 21. Internal tTIME-OUT Initiates New Cycle After
Failure to Detect Valley Voltage
(with 5µs Delay for FAN6300H version)
www.fairchildsemi.com
11
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| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet FAN6300A.PDF ] | |
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