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PDF OZ826 Data sheet ( Hoja de datos )
| Número de pieza | OZ826 | |
| Descripción | Dual-Phase DC-DC Controller | |
| Fabricantes | O2Micro International | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de OZ826 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
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OZ826
Dual-Phase DC-DC Controller for AMD Mobile CPU
FEATURES
• Dual-phase DC-DC controller with integrated drivers
• 6 bit AMD VID codes compatible
• 1% output voltage accuracy
• 6V to 24V input supports 2s to 5s battery power
• Voltage Feed-Forward Compensation
• High efficiency, up to 94%
• High light-load efficiency: 80% at 200mA
• Non-audio skip mode
• Constant Ripple-Current topology facilitates optimum
inductor size
• Supports 60A output current
• Ultra-fast transient recovery
• Adjustable load line support
• Slew control at start-up and OTF VID changes
• True differential output voltage remote sensing
• AMD compliant Power Good signal
• VIN & VDDA Undervoltage Lockout Protection
• Latched over-voltage protection
• Cycle-by-cycle Overcurrent protection with latched
timeout
• Small, thin 5x5 QFN32 package
APPLICATIONS
Notebook CPU power supplies
ORDERING INFORMATION
Part Number
OZ826LN
Temp Range
0oC to 85oC
Package
32 QFN 5x5mm
GENERAL DESCRIPTION
OZ826 is a DC/DC controller specifically developed to
support the design of power supplies for AMD mobile
microprocessors supporting the 6 bit VID codes (see Table
1). Its high efficiency under both light and heavy load
conditions, DC accuracy, remote voltage sensing and
excellent transient response make it a good choice for low
voltage CPUs.
The core topology is based on a constant-ripple current
sync-buck controller with integrated drivers. The voltage
feed-forward compensation ensures a high rejection of
input voltage transients.
Overvoltage Protection (OVP) acts when the output voltage
exceeds the 1.8V threshold. This protection condition is
latched and the shutdown occurs. After an OVP event, the
EN pin should be toggled or VDDA cycled to restart the
circuit.
Under Voltage Lockout (UVLO) circuit monitors both VDDA
and VIN. Shut down occurs when VDDA falls below 4.2V
or VIN is less than typically 4.8V.
The output is protected against overload by a cycle-by-
cycle Overcurrent Protection (OCP) circuit. Its limit is user-
adjustable. Maximum OCP timeout is typically 1ms.
The Power Good (PG) signal is open drain unless the
output voltage drops more than 250mV off the set VID.
At start-up the output voltage ramps up in a controlled
manner with an externally adjustable slew rate.
SIMPLIFIED APPLICATION DIAGRAM
PIN DIAGRAM
www.DataSheet4U.com
07/31/08
Copyright © 2005-2008 by O2Micro
Patent #6,844,710
OZ826-SF-v1.0
All Rights Reserved
Page 1
1 page  
PACKAGE INFORMATION - 32 PIN QFN
Exposed pad is GNDA (pin 33) and must be soldered to PCB
OZ826
11
22
33
www.DataSheet4U.com
Rth j-a (QFN-32 5x5mm package) = 26ºC/W
OZ826-SF-v1.0
Page 5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet OZ826.PDF ] | |
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