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PDF A3PE600L Data sheet ( Hoja de datos )
| Número de pieza | A3PE600L | |
| Descripción | Military ProASIC3/EL Low-Power Flash FPGAs | |
| Fabricantes | Actel Corporation | |
| Logotipo |  |
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v1.0
Military ProASIC3/EL Low-Power Flash FPGAs
with Flash*Freeze Technology
®
Features and Benefits
Military Temperature Tested and Qualified
• Each Device Tested from –55°C to 125°C
Firm-Error Immune
• Not Susceptible to Neutron-Induced Configuration Loss
Low Power
• Dramatic Reduction in Dynamic and Static Power
• 1.2 V to 1.5 V Core and I/O Voltage Support for Low Power†
• Low Power Consumption in Flash*Freeze Mode Allows for
Instantaneous Entry To / Exit From Low-Power Flash*Freeze
Modeƒ
• Supports Single-Voltage System Operation
• Low-Impedance Switches
High Capacity
• 600 k to 3 M System Gates
• Up to 504 kbits of True Dual-Port SRAM
• Up to 620 User I/Os
Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
• Live-at-Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered Off
High Performance
• 350 MHz (1.5 V systems) and 250 MHz (1.2 V systems) System
Performance
• 3.3 V, 66 MHz, 66-Bit PCI (1.5 V systems) and 66 MHz, 32-Bit
PCI (1.2 V systems)
In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption via JTAG (IEEE 1532–compliant)
• FlashLock® to Secure FPGA Contents
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
• High-Performance, Low-Skew Global Network
• Architecture Supports Ultra-High Utilization
Table 1-1 • Military ProASIC3/EL Low-Power Devices
ProASIC3/EL Devices
ARM Cortex-M1 Devices1
A3PE600L
System Gateswww.DataSheet4U.net
VersaTiles (D-flip-flops)
RAM kbits (1,024 bits)
600 k
13,824
108
4,608-Bit Blocks
FlashROM Bits
Secure (AES) ISP2
Integrated PLL in CCCs
24
1k
Yes
6
VersaNet Globals
18
I/O Banks
Maximum User I/Os
Package Pins
8
270
PQFP
FBGA
FG484
Notes:
1. Refer to the Cortex-M1 product brief for more information.
2. AES is not available for ARM-enabled ProASIC3/EL devices.
Advanced and Pro (Professional) I/Os††
•
•
700 Mbps DDR,
1.2 V, 1.5 V, 1.8
LVDS-Capable I/Os
V, 2.5 V, and 3.3 V Mixed-Voltage
Operation†
• Bank-Selectable I/O Voltages—up to 8 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X, and
LVCMOS 2.5 V / 5.0 V Input†
• Differential I/O Standards: LVPECL, LVDS, BLVDS, and M-LVDS
• Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL
2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3
Class I and II (A3PE3000L only)
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold-Sparing I/Os
• Programmable Output Slew Rate and Drive Strength
• Programmable Input Delay (A3PE3000L only)
• Schmitt Trigger Option on Single-Ended Inputs (A3PE3000L)
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the Military ProASIC®3EL
Family
Clock Conditioning Circuit (CCC) and PLL
• Six CCC Blocks, One with Integrated PLL (ProASIC3) and All
with Integrated PLL (ProASIC3EL)
• Configurable Phase Shift, Multiply/Divide, Delay
Capabilities, and External Feedback
• Wide Input Frequency Range 1.5 MHz to 250 MHz (1.2 V
systems) and 350 MHz (1.5 V systems)
SRAMs and FIFOs
• Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9,
and ×18 organizations available)
• True Dual-Port SRAM (except ×18)
• 24 SRAM and FIFO Configurations with Synchronous
Operation:
– 250 MHz: For 1.2 V Systems
ARM– ®35P0roMcHezs:sFoorr
1.5 V Systems
Support in
ProASIC3/EL
FPGAs
• ARM Cortex™-M1 Soft Processor Available with or without
Debug
A3P1000
M1A3P1000
1M
24,576
144
32
1k
Yes
1
18
4
154
A3PE3000L
M1A3PE3000L
3M
75,264
504
112
1k
Yes
6
18
8
620
PQ208
FG144
FG484, FG896
† A3P1000 only supports 1.5 V core operation.
ƒ Flash*Freeze technology is not available for A3P1000.
†† Pro I/Os are not available on A3P1000.
August 2008
© 2008 Actel Corporation
i
1 page  
1 – Military ProASIC3/EL Device Family Overview
General Description
The military ProASIC3/EL family of Actel flash FPGAs dramatically reduces dynamic power
consumption by 40% and static power by 50%. These power savings are coupled with
performance, density, true single chip, 1.2 V to 1.5 V core and I/O operation, reprogrammability,
and advanced features.
Actel's proven Flash*Freeze technology enables military ProASIC3EL device users to shut off
dynamic power instantaneously and switch the device to static mode without the need to switch
off clocks or power supplies, and retaining internal states of the device. This greatly simplifies
power management. In addition, optimized software tools using power-driven layout provide
instant push-button power reduction.
Nonvolatile flash technology gives military ProASIC3/EL devices the advantage of being a secure,
low-power, single-chip solution that is live at power-up (LAPU). Military ProASIC3/EL devices offer
dramatic dynamic power savings, giving FPGA users flexibility to combine low power with high
performance.
These features enable designers to create high-density systems using existing ASIC or FPGA design
flows and tools.
Military ProASIC3/EL devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM
storage as well as clock conditioning circuitry (CCC) based on an integrated phase-locked loop
(PLL). Military ProASIC3/EL devices support devices from 600 k system gates to 3 million system
gates with up to 504 kbits of true dual-port SRAM and 620 user I/Os.
M1 military ProASIC3/EL devices support the high-performance, 32-bit Cortex-M1 processor
developed by ARM for implementation in FPGAs. ARM Cortex-M1 is a soft processor that is fully
implemented in the FPGA fabric. It has a three-stage pipeline that offers a good balance between
low-power consumption and speed when implemented in an M1 military ProASIC3/EL device. The
processor runs the ARMv6-M instruction set, has a configurable nested interrupt controller, and can
be implemented with or without the debug block. ARM Cortex-M1 is available at no cost from
Actel for use in M1 military ProASIC3/ELFPGAs.
The ARM-enabled devices have Actel ordering numbers that begin with M1 and do not support
AES decryption.
www.DataSheet4U.net
Flash*Freeze Technology†
Military ProASIC3EL devices offer Actel's proven Flash*Freeze technology, which allows
instantaneous switching from an active state to a static state. When Flash*Freeze mode is
activated, military ProASIC3EL devices enter a static state while retaining the contents of registers
and SRAM. Power is conserved without the need for additional external components to turn off
I/Os or clocks. Flash*Freeze technology is combined with in-system programmability, which enables
users to quickly and easily upgrade and update their designs in the final stages of manufacturing
or in the field. The ability of military ProASIC3EL devices to support a 1.2 V core voltage allows for
an even greater reduction in power consumption, which enables low total system power.
When the military ProASIC3EL device enters Flash*Freeze mode, the device automatically shuts off
the clocks and inputs to the FPGA core; when the device exits Flash*Freeze mode, all activity
resumes and data is retained.
The availability of low-power modes, combined with a reprogrammable, single-chip, single-voltage
solution, make military ProASIC3EL devices suitable for low-power data transfer and manipulation
in military-temperature applications where available power may be limited (e.g., in battery-
powered equipment); or where heat dissipation may be limited (e.g., in enclosures with no forced
cooling).
† Flash*Freeze technology is not supported on A3P1000.
v1.0
1-1
5 Page 
Military ProASIC3/EL Device Family Overview
www.DataSheet4U.net
The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs
located near the CCC that have dedicated connections to the CCC block.
The CCC block has these key features:
• Wide input frequency range (fIN_CCC) = 1.5 MHz up to 250 MHz
• Output frequency range (fOUT_CCC) = 0.75 MHz up to 250 MHz
• 2 programmable delay types for clock skew minimization
• Clock frequency synthesis
Additional CCC specifications:
• Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output
divider configuration.
• Output duty cycle = 50% ± 1.5% or better
• Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single
global network used
• Maximum acquisition time is 300 µs
• Exceptional tolerance to input period jitter—allowable input jitter is up to 1.5 ns
• Four precise phases; maximum misalignment between adjacent phases of 40 ps × 250 MHz /
fOUT_CCC
Global Clocking
Military ProASIC3/EL devices have extensive support for multiple clocking domains. In addition to
the CCC and PLL support described above, there is a comprehensive global clock distribution
network.
Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three
quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the
core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for
rapid distribution of high-fanout nets.
I/Os with Advanced I/O Standards
The military ProASIC3/EL family of FPGAs features a flexible I/O structure, supporting a range of
voltages (1.5 V, 1.8 V, 2.5 V, and 3.3 V). In addition, 1.2 V I/O operation is supported for military
ProASIC3EL devices. Military ProASIC3/EL FPGAs support different I/O standards, including single-
ended, differential, and voltage-referenced (military ProASIC3EL). The I/Os are organized into
banks, with two, four, or eight (military ProASIC3EL only) banks per device. The configuration of
these banks determines the I/O standards supported. For military ProASIC3EL, each I/O bank is
subdivided into VREF minibanks, which are used by voltage-referenced I/Os. VREF minibanks contain
8 to 18 I/Os. All the I/Os in a given minibank share a common VREF line. Therefore, if any I/O in a
given VREF minibank is configured as a VREF pin, the remaining I/Os in that minibank will be able to
use that reference voltage.
Each I/O module contains several input, output, and enable registers. These registers allow the
implementation of the following:
• Single-data-rate applications (e.g., PCI 66 MHz, bidirectional SSTL 2 and 3, Class I and II)
• Double-data-Rate applications (e.g., DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point
communications, and DDR 200 MHz SRAM using bidirectional HSTL Class II).
Military ProASIC3EL banks support LVPECL, LVDS, B-LVDS, and M-LVDS. B-LVDS and M-LVDS can
support up to 20 loads.
Part Number and Revision Date
Part Number 51700106-001-0
Revised August 2008
v1.0
1-7
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet A3PE600L.PDF ] | |
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