P5CC073UA Datasheet PDF - NXP Semiconductors
| Part Number | P5CC073UA | |
| Description | Secure dual interface and contact PKI smart card controller | |
| Manufacturers | NXP Semiconductors | |
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P5Cx012/02x/40/73/80/144
family
Secure dual interface and contact PKI smart card controller
Rev. 03 — 24 January 2008
Objective short data sheet
1. General description
www.DataSheet4U.net
1.1 SmartMX family approach
The new CMOS14 SmartMX family members feature a modular set of devices with:
• 12 KB to 144 KB EEPROM
• 200 KB user ROM
• 6144 B RAM
• High-performance secured Public Key Infrastructure (PKI) coprocessor (RSA, ECC)
• Secured dual/triple-DES coprocessor
• Secured AES coprocessor
• Memory Management Unit (MMU)
• ISO/IEC 7816 contact interface
• Optional ISO/IEC 14443 A Contactless Interface Unit (CIU)
• Optional S2C interface for NFC communication link
• 5-metal-layer 0.14 µm CMOS technology
• EEPROM with typical 500000 cycles endurance and minimum 20 years retention time
• Broad spectrum of delivery types
• Optional certified crypto library modules for RSA, ECC, DES, AES, SHA and PRNG
1.2 SmartMX family properties
The long-term approved SmartMX family features a significantly enhanced secure smart
card IC architecture. Extended instructions for Java and C code, linear addressing, high
speed at low power and a universal memory management unit are among many other
improvements added to the classic 80C51 core architecture. The technology transfer step
from 5-metal-layer 0.18 µm to 5-metal-layer 0.14 µm CMOS technology offers now even
more advantages in terms of security features, memory resources, crypto coprocessor
calculation speed for RSA and ECC as well as availability of secure hardware support for
2/3-key Digital Encryption Standard (DES) and Advanced Encryption Standard (AES)
operations.
The availability of contact interface, optional contactless or S2C interface enables the easy
implementation of native or open platform and multi-application operating systems in
market segments like e.g. banking, E-passport, ID card, Health Card, secure access, Java
card, Near Field Communication (NFC) connectable mobile hand sets as well as Trusted
Platform Modules (TPM).
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NXP Semiconductors
P5Cx012/02x/40/73/80/144 family
Secure dual interface and contact PKI smart card controller
2. Features
• Common criteria CC EAL5+ certification planned [except ECC over GF(2n)] according
to BSI-PP-0002 protection profile
www.DataSheet4U.net
2.1 Standard family features
I EEPROM: choice of 12 KB, 20 KB, 40 KB, 72 KB, 80 KB or 144 KB
N Data retention time: 20 years minimum
N Endurance: 500000 cycles typical
I ROM: 200 KB
I RAM: 6144 B
N 256 B IRAM + 3.25 KB standard RAM usable for CPU
N 2560 B FXRAM usable for FameXE
I Dedicated Secure_MX51 Smart Card CPU (Memory eXtended/enhanced 80C51)
N 5-metal-layer 0.14 µm CMOS technology
N Operating in Contact and Contactless mode (dependent on family type option)
N Featuring a 24-bit universal memory space, 24-bit program counter
N Combined universal program and data linear address range up to 16 MB
N Additional instructions to improve:
- Pointer operations
- Performance
- Code density of both C and Java source code
I ISO/IEC 7816 contact interface
I PKI coprocessor FameXE
I Support of major Public Key Cryptography (PKC) systems like RSA, Elgamel, DSS,
Diffie-Hellman, Guillou-Quisquater, Fiat-Shamir and Elliptic Curves
N 8192 bits maximum key length for RSA with randomly chosen modulus
N 4096 bits maximum key length for calculation within RAM
N 32-bit interface
N Boolean operations for acceleration of standard, symmetric cipher algorithms
I High speed Triple-DES coprocessor (64-bit parallel processing DES engine)
N Two or three keys loadable
N DES3 performance < 40 µs
I High speed AES coprocessor (128-bit parallel processing AES engine)
I Memory Management Unit (MMU)
I Low power and low voltage design using NXP Semiconductors handshaking
technology
I Multiple source vectorized interrupt system with four priority levels
I Watch exception provides software debugging facility
I Multiple source RESET system
I Two 16-bit timers
I High reliable EEPROM for both data storage and program execution
I Bytewise EEPROM programming and read access
P5CX012_02X_40_73_80_144_FAM_SDS_3
Objective short data sheet
Rev. 03 — 24 January 2008
© NXP B.V. 2008. All rights reserved.
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| Information | Total 18 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ P5CC073UA.PDF Datasheet ] | |
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