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PDF H27UAG8T2A Data sheet ( Hoja de datos )
| Número de pieza | H27UAG8T2A | |
| Descripción | 16 Gbit (2048 M x 8 bit) NAND Flash | |
| Fabricantes | Hynix | |
| Logotipo |  |
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1
Preliminary
H27UAG8T2A Series
16 Gbit (2048 M x 8 bit) NAND Flash
16 Gb NAND Flash
H27UAG8T2A
www.DataSheet4U.net
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 0.5 / Jul. 2009
1
1 page  
1
Preliminary
H27UAG8T2A Series
16 Gbit (2048 M x 8 bit) NAND Flash
CE
WE
RE
ALE
CLE
WP
VCC
IO0~IO7
R/B
IO7 - IO0
CLE
ALE
CE
RE
WE
WP
R/B
Vcc
Vss
NC
Data Input / Outputs
Command latch enable
Address latch enable
Chip Enable
Read Enable
Write Enable
Write Protect
Ready / Busy
Power Supply
Ground
No Connection
VSS
Figure 1 : Logic Diagram
Table 1 : Signal Names
www.DataSheet4U.net
1&
1&
1&
1&
1&
1&
5%
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9FF
9VV
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1&
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1&
1&
1&
1&
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7623
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,2
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9FF
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,2
,2
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Figure 2 : 48-TSOP1 Contact, x8 Device
Rev 0.5 / Jul. 2009
5
5 Page 
1
Preliminary
H27UAG8T2A Series
16 Gbit (2048 M x 8 bit) NAND Flash
3.3 Page Program
The device is programmed by page. The number of consecutive partial page programming operation within the same page
without an intervening erase operation must not exceed 1 times. The addressing should be done in sequential order in a
block. A page program cycle consists of a serial data loading period in which up to 4,320 bytes of data may be loaded into
the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate
cell. The serial data loading period begins by inputting the Serial Data Input command (80h), followed by the five cycle ad-
dress inputs and then serial data. The words other than those to be programmed do not need to be loaded. The device sup-
ports random data input in a page. The column address of next data, which will be entered, may be changed to the address
which follows random data input command (85h). Random data input may be operated multiple times regardless of how
many times it is done in a page. The Page Program confirm command (10h) initiates the programming process. Writing 10h
alone without previously entering the serial data will initiate the programming process anyway. The internal write state con-
troller automatically executes the algorithms and timings necessary for program and verify, thereby freeing the system con-
troller for other tasks. Once the program process starts, the Read Status Register command may be entered to read the status
register.
The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit I/O<6>
(busy/ready bit) of the Status Register (70h or F1h). Only the Read Status command and Reset command are valid while
programming is in progress. When the Page Program is complete, the Write Status Bit I/O<0> (pass/fail) may be checked.
The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s.
The command register remains in Read Status command mode until another valid command is written to the command
register. Figure 15 details the sequence.
NOTE : the device support program operation with 2kByte data to offer the backward compatibility to the controller
which uses the Nand with 2Kbyte page.
3.4 Multi Plane Program
Device supports multiple-plane program: it is possible to program in parallel 2 pages, one per each plane. Page and block
address for the two pages must be the same .
A multiple plane program cycle consists of a double serial data loading period in which up to 8,640bytes of data may be
loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into the
appropriate cell.
The serial data loading period begins by inputting the Serial Data Input command (80h), followed by the five cycle address
inputs and then serial data for the 1st page. Address for this page must be within 1st plane (A<20>=0). The data of 1st page
other than those to be programmed do not need to be loaded.
The device supports random data input exactly like page program operation. The Dummy Page Program Confirm command
(11h) stops 1st page data input and the device becomes busy for a short time (tDBSY).
Once it has become ready again, 81h command must be issued, followed by 2nd page address (5 cycles) and its serial data
input. Address for this page must be within 2nd plane (A<20>=1);the data of 2nd page other than those to be programmed
do not need to be loaded.
Program Confirm command (10h) initiates parallel programming of both pages .
User canwww.DataSheet4U.net check operation status by R/B pin or read status register commands (70h or F1h).
If user opts for 70h, Status register read will provide a "global" information about the operation in the two planes (IO<6>=
ready / busy, IO<0> = pass / fail)
If user opts for F1h, Status register read will provide information about the operation in each of the two planes (IO<0> :
Global pass/fail, IO<1>: Plane0 pass/fail, IO<2>: Plane1 pass/fail).
Please note that only Reset (FFh) or Status register commands (70h / F1h) can be issued during Dummy Busy time (tDBSY);
in the latter case please refer to Status register command section for further information.
Multi-plane program sequence is described in Figure 16.
Grey area :
a) Please note that page and block address for the pages in the two planes must be the same. If the user fails to do so
the device will program the data in location based on the page and block address of the page issued during the sequence
81h - 10h.
b) plane order in the command sequence can be swapped; in other words, user may input first the data of the page in
plane 1 (A20=1) and then the data of the corresponding page in plane 0 (A20=0)
Rev 0.5 / Jul. 2009
11
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