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ML12210 데이터시트 PDF




LANSDALE Semiconductor에서 제조한 전자 부품 ML12210은 전자 산업 및 응용 분야에서
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부품번호 ML12210 기능
기능 Serial Input PLL Frequency Synthesizer
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ML12210 데이터시트, 핀배열, 회로
ML12210
Serial Input PLL
Frequency Synthesizer
Legacy Device: Motorola MC12210
The ML12210 is a 2.5 GHz Bipolar monolithic serial input
phase locked loop (PLL) synthesizer with pulse–swallow function.
It is designed to provide the high frequency local oscillator signal
of an RF transceiver in handheld communication applications.
The technology used allows for low power operation at a mini-
mum supply voltage of 2.7 V. The device is designed for operation
over 2.7 to 5.5 V supply range for input frequencies up to 2.5 GHz
with a typical current drain of 9.5 mA. The low power consump-
tion makes the ML12210 ideal for handheld battery operated
applications such as cellular or cordless telephones, wireless LAN
or personal communication services. A dual modulus prescaler is
integrated to provide either a 32/33 or 64/65 divide ratio.
• Low Power Supply Current of 8.8 mA Typical for ICC
and 0.7 mA Typical for Ip
• Supply Voltage of 2.7 to 5.5 V
• Dual Modulus Prescaler With Selectable Divide Ratios
of 32/33 or 64/65
• On–Chip Reference Oscillator/Buffer
• Programmable Reference Divider Consisting of a
Binary 14–Bit Programmable Reference Counter
• Programmable Divider Consisting of a Binary 7–Bit
Swallow Counter and an 11–Bit Programmable Counter
• Phase/Frequency Detector With Phase Conversion Function
• Balanced Charge Pump Outputs
• Dual Internal Charge Pumps for Bypassing the First
Stage of the Loop Filter to Decrease Lock Time
• Outputs for External Charge Pump
• Operating Temperature Range of TA = –40 to 85°C
NOTE: Also available is the ML12202, a 1.1 GHz version of this
function.
16
1
SO 16 = -5P
PLASTIC PACKAGE
CASE 751B
(SO–16)
CROSS REFERENCE/ORDERING INFORMATION
PACKAGE MOTOROLA LANSDALE
SO 16
MC12210D ML12210-5P
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
MAXIMUM RATINGS (Note 1)
Parameter
Power Supply Voltage, Pin 4
Symbol
VCC
Value
–0.5 to 6.0
Unit
Vdc
Power Supply Voltage, Pin 3
Vp VCC to 6.0 Vdc
Storage Temperature Range
Tstg
–65 to 150
°C
NOTES: 1. Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation should be restricted to the Recommended
Operating Conditions.
www.DataSheet4U.com
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Issue A




ML12210 pdf, 반도체, 판매, 대치품
ML12210
LANSDALE Semiconductor, Inc.
DATA ENTRY FORMAT
The three wire interface of DATA pin, CLK (clock) pin and LE (load enable) pin controls the serial data input of the 14–bit programma-
ble reference divider plus the prescaler setting bit, and the 18–bit programmable divider. A rising edge of the clock shifts one bit of serial
data into the internal shift registers. Depending upon the level of the control bit, stored data is transferred into the latch when load enable
pin is HIGH or OPEN.
Control bit: “H” = data is transferred into 15–bit latch of programmable reference divider
“L” = data is transferred into 18–bit latch of programmable divider
WARNING: Switching CLK or DATA after the device is programmed may generate noise on the charge pump outputs which will affect
the VCO.
PROGRAMMABLE REFERENCE DIVIDER
16–bit serial data format for the programmable reference counter, “R–counter”, and prescaler select bit (SW) is shown below. If the con-
trol bit is HIGH, data is transferred from the 15–bit shift register into the 15–bit latch which specifies the R divide ratio (8 to16383) and
the prescaler divide ratio (SW=0 for ÷64/65, SW=1 for ÷32/33). An R divide ratio less than 8 is prohibited.
For Control bit (C) = HIGH:
SETTING BIT FOR PRESCALER DIVIDE RATIO (FIRST BIT)
MSB
CONTROL BIT (LAST BIT)
LSB
SRRRRRRRRRRRRRRC
W 14 13 12 11 10 9 8 7 6 5 4 3 2 1
SETTING BITS FOR DIVIDE RATIO OF PROGRAMMABLE
REFERENCE COUNTER (R–COUNTER)
DIVIDE RATIO OF PROGRAMMABLE REFERENCE (R) COUNTER
Divide R R R R R R R R R R R R R R
Ratio R
14
13
12
11
10
9
8
7
6
5
4
3
2
1
8 00000000001000
9 00000000001001
• ••••••••••••••
16383 1 1 1 1 1 1 1 1 1 1 1 1 1 1
PRESCALER SELECT BIT
Prescaler Divide Ratio P
64/65
32/33
SW
0
1
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ML12210 전자부품, 판매, 대치품
ML12210
LANSDALE Semiconductor, Inc.
For FC = HIGH:
fr lags fp in phase OR fp>fr in frequency
When the phase of fr lags that of fp or the frequency of fp is greater than fr, the φP output will remain in a HIGH state while the φR out-
put will pulse from LOW to HIGH. The output pulse will reach a minimum 50% duty cycle under a 180° out of phase condition. The sig-
nal on φR indicates to the VCO to decrease in frequency to bring the loop into lock.
fr leads fp in phase OR fp<fr in frequency
When the phase of fr leads that of fp or the frequency of fp is less than fr, the φR output will remain in a LOW state while the φP output
pulses from HIGH to LOW. The output pulse will reach a minimum 50% duty cycle under a 180° out of phase condition. The signal on
φP indicates to the VCO to increase in frequency to bring the loop to lock.
fr = fp in phase and frequency
When the phase and frequency of fr and fp are equal, the output φP will remain in a HIGH state and φR will remain in a LOW state
except for voltage spikes when signals are in phase. This situation indicates that the loop is in lock and the phase comparator will main-
tain the loop in its locked state.
When FC = LOW, the operation of the phase comparator is reversed from the above explanation.
For FC = LOW:
fr lags fp in phase OR fp>fr in frequency
When the phase of fr lags that of fp or the frequency of fp is greater than fr, the φR output will remain in a LOW state while the φP out-
put will pulse from HIGH to LOW. The output pulse will reach a minimum 50% duty cycle under a 180° out of phase condition. The sig-
nal on φP indicates to the VCO to increase in frequency to bring the loop into lock.
fr leads fp in phase OR fp<fr in frequency
When the phase of fr leads that of fp or the frequency of fp is less than fr, the φP output will remain in a HIGH state while the φR output
pulses from LOW to HIGH. The output pulse will reach a minimum 50% duty cycle under a 180° out of phase condition. The signal on
φR indicates to the VCO to decrease in frequency to bring the loop to lock.
fr = fp in phase and frequency
When the phase and frequency of fr and fp are equal, the output φP will remain in a HIGH state and φR will remain in a LOW state
except for voltage spikes when signals are in phase. This situation indicates that the loop is in lock and the phase comparator will main-
tain the loop in its locked state.
The FC pin controls not only the phase characteristics, but also controls the fOUT test pin. The FC pin permits the user to monitor either
of the phase comparator input signals, fr or fp, at the fOUT output providing a test mode where the programming of the dividers and the
output of the counters can be checked. When FC is HIGH, fOUT = fr, the programmable reference divider output. When FC is LOW,
fOUT = fp, the programmable divider output.
Hence,
If VCO characteristics are like (1), FC should be set HIGH or OPEN.
If VCO characteristics are like (2), FC should be set LOW.
fOUT = fr
fOUT = fp
Figure 4. VCO Characteristics
(1)
VCO INPUT VOLTAGE
(2)
Figure 5. Phase Comparator, Internal Charge Pump, and
fOUT Characteristics
FC = HIGH or OPEN
FC = LOW
Do φR φP fOUT Do φR φP fOUT
fp < fr H L L fr L H H fp
fp > fr L H H fr H L L fp
fp = fr Z L H fr Z L H fp
NOTES: Z = High impedance
When LE is HIGH or Open, BISW has the same
characteristics as Do.
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관련 데이터시트

부품번호상세설명 및 기능제조사
ML12210

Serial Input PLL Frequency Synthesizer

LANSDALE Semiconductor
LANSDALE Semiconductor

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