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PDF L4C381JC20 Data sheet ( Hoja de datos )
| Número de pieza | L4C381JC20 | |
| Descripción | 16-bit Cascadable ALU | |
| Fabricantes | LOGIC Devices Incorporated | |
| Logotipo |  |
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DEVICES INCORPORATED
DEVICES INCORPORATED
L4C381
16-bit CaLsc4adCab3le8A1LU
16-bit Cascadable ALU
FEATURES
DESCRIPTION
u High-Speed (15ns), Low Power
16-bit Cascadable ALU
u Implements Add, Subtract, Accumu-
late, Two’s Complement, Pass, and
Logic Operations
u All Registers Have a Bypass Path
for Complete Flexibility
u 68-pin PLCC, J-Lead
L4C381 BLOCK DIAGRAM
A15-A0
16
ENA
A REGISTER
The L4C381 is a flexible, high speed,
cascadable 16-bit Arithmetic and
Logic Unit. It combines four 381-type
4-bit ALUs, a look-ahead carry
generator, and miscellaneous interface
logic — all in a single 68-pin package.
While containing new features to
support high speed pipelined architec-
tures and single 16-bit bus configura-
tions, the L4C381 retains full perform-
ance and functional compatibility with
the bipolar ’381 designs.
The L4C381 can be cascaded to
perform 32-bit or greater operations.
See “Cascading the L4C381” toward
B15-B0
16
B REGISTER
ENB
the end of this data sheet for more
information.
ARCHITECTURE
The L4C381 operates on two 16-bit
operands (A and B) and produces a
16-bit result (F). Three select lines
control the ALU and provide 3
arithmetic, 3 logical, and 2 initializa-
tion functions. Full ALU status is
provided to support cascading to
longer word lengths. Registers are
provided on both the ALU inputs and
the output, but these may be bypassed
under user control. An internal
feedback path allows the registered
ALU output to be routed to one of the
ALU inputs, accommodating chain
operations and accumulation. Fur-
thermore, the A or B input can be
forced to Zero allowing unary func-
tions on either operand.
ALU OPERATIONS
00
P, G, C16
OVF, Z
5
ALU
16
RESULT REGISTER
FTF
OE
CLK
16
TO ALL REGISTERS
16
F15-F0
FTAB
2
OSA
OSB
4
S2-S0, C0
ENF
The S2–S0 lines specify the operation
to be performed. The ALU functions
and their select codes are shown in
Table 1.
The two functions, B minus A and
A minus B, can be achieved by setting
the carry input of the least significant
slice and selecting codes 001 and 010
respectively.
TABLE 1. ALU FUNCTIONS
S2-S0
FUNCTION
000 CLEAR (F = 00 • • • 00)
001 NOT(A) + B
010 A + NOT(B)
011 A + B
100 A XOR B
101 A OR B
110 A AND B
111 PRESET (F = 11 • • • 11)
Arithmetic Logic Units
1 08/16/2000–LDS.381-P
1 page  
DEVICES INCORPORATED
L4C381
16-bit Cascadable ALU
SWITCHING CHARACTERISTICS — COMMERCIAL OPERATING RANGE (0°C to +70°C)
GUARANTEED MAXIMUM COMBINATIONAL DELAYS Notes 9, 10 (ns)
To Output
L4C381-20
L4C381-15
From Input
FTAB = 0, FTF = 0
Clock
C0
S2-S0, OSA, OSB
F15-F0 P, G OVF, Z C16 F15-F0 P, G OVF, Z C16
11 20 20 20 11 15 15 15
— — 14 14 — — 13 13
— 18 20 18 — 14 15 14
FTAB = 0, FTF = 1
Clock
C0
S2-S0, OSA, OSB
20 20 20 20 15 15 15 15
18 — 14 14 14 — 13 13
20 18 20 18 15 14 15 14
FTAB = 1, FTF = 0
A15-A0, B15-B0
Clock
C0
S2-S0, OSA, OSB
— 16 20 17 — 14 15 14
11 — — — 11 — — —
— — 14 14 — — 13 13
— 18 20 18 — 14 15 14
FTAB = 1, FTF = 1
A15-A0, B15-B0
20 16 20 17 15 14 15 14
Clock (OSA, OSB = 0) 20 20 20 20 15 15 15 15
C0 18 — 14 14 14 — 13 13
S2-S0, OSA, OSB
20 18 20 18 15 14 15 14
GUARANTEED MINIMUM SETUP AND HOLD TIMES WITH RESPECT TO CLOCK RISING EDGE Notes 9, 10 (ns)
L4C381-20
L4C381-15
FTAB = 0 FTAB = 1 FTAB = 0 FTAB = 1
Input
Setup Hold Setup Hold Setup Hold Setup Hold
A15-A0, B15-B0
5 0 14 0
5 0 12 0
C0
12 0
12 0
10 0
10 0
S2-S0, OSA, OSB
15 0
15 0
12 0
12 0
ENA, ENB, ENF
50
50
50
50
TRI-STATE ENABLE/DISABLE TIMES Notes 9, 10, 11 (ns)
L4C381-20 L4C381-15
tENA
8
6
tDIS 8
6
CLOCK CYCLE TIME AND PULSE WIDTH Notes 9, 10 (ns)
L4C381-20 L4C381-15
Minimum Cycle Time
18
14
Highgoing Pulse
5
4
Lowgoing Pulse
5
4
Arithmetic Logic Units
5 08/16/2000–LDS.381-P
5 Page 
DEVICES INCORPORATED
FIGURE 4C. FTAB = 1, FTF = 0
From
To
Clock
©F
A, B © Other
C0 © Other
S2-S0, OSA, OSB
© Other
A, B Setup time
C0 Setup time
S2-S0, OSA, OSB
Setup time
ENA, ENB, ENF
Setup time
Minimum cycle time
(F register accumulate loop)
L4C381
16-bit Cascadable ALU
Calculated Specification Limit
= Same as 16-bit case
= (A, B © C16) + (C0 © Out)
= (C0 © C16) + (C0 © Out)
= (S2-S0, OSA, OSB © C16) + (C0 © Out)
= (A, B © C16) + (C0 Setup time)
= (C0 © C16) + (C0 Setup time)
= (S2-S0, OSA, OSB © C16) + (C0 Setup time)
= Same as 16-bit case
= (Clock © C16) + (C0 Setup time)
MOST
SIGNIFICANT
SLICE
A31-A16
B31-B16
AB
F C0
D
Q
16
CLOCK
F31-F16
A15-A0
B15-B0
AB
C16 F
C0
C0, S0–S 2
OSA, OSB
D
Q
16
F15-F0
CLOCK
LEAST
SIGNIFICANT
SLICE
FIGURE 4D. FTAB = 1, FTF = 1
From
To
A, B © F
A, B © Other
C0
C0
S2-S0, OSA, OSB
S2-S0, OSA, OSB
©F
© Other
©F
© Other
A, B Setup time
C0 Setup time
S2-S0, OSA, OSB
Setup time
ENA, ENB, ENF
Setup time
Minimum cycle time
(F register accumulate loop)
MOST
SIGNIFICANT
SLICE
A31-A16
B31-B16
A
F
16
B
C0
F31-F16
Calculated Specification Limit
= (A, B © C16) + (C0 © F)
= (A, B © C16) + (C0 © Out)
= (C0 © C16) + (C0 © F)
= (C0 © C16) + (C0 © Out)
= (S2-S0, OSA, OSB © C16) + (C0 © F)
= (S2-S0, OSA, OSB © C16) + (C0 © Out)
= (A, B © C16) + (C0 Setup time)
= (C0 © C16) + (C0 Setup time)
= (S2-S0, OSA, OSB © C16) + (C0 Setup time)
= Same as 16-bit case
= (Clock © C16) + (C0 Setup time)
A15-A0
B15-B0
A
C16 F
16
B
C0
F15-F0
C0, S0–S 2
OSA, OSB
LEAST
SIGNIFICANT
SLICE
Arithmetic Logic Units
11 08/16/2000–LDS.381-P
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet L4C381JC20.PDF ] | |
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