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PDF AD9146 Data sheet ( Hoja de datos )
| Número de pieza | AD9146 | |
| Descripción | TxDAC Digital-to-Analog Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
Dual, 16-Bit, 1230 MSPS,
TxDAC+ Digital-to-Analog Converter
AD9146
FEATURES
Flexible LVDS interface allows byte or nibble load
Single-carrier W-CDMA ACLR = 80 dBc at 122.88 MHz IF
Analog output: adjustable 8.7 mA to 31.7 mA, RL = 25 Ω to 50 Ω
Integrated 2×/4× interpolator/complex modulator allows
carrier placement anywhere in the DAC bandwidth
Gain, dc offset, and phase adjustment for sideband
suppression
Multiple chip synchronization interfaces
High performance, low noise PLL clock multiplier
Digital inverse sinc filter
Low power: 1.2 W at 1.0 GSPS, 800 mW at 500 MSPS,
full operating conditions
48-lead, exposed paddle LFCSP
APPLICATIONS
Wireless infrastructure
W-CDMA, CDMA2000, TD-SCDMA, WiMAX, GSM, LTE
Digital high or low IF synthesis
Transmit diversity
Wideband communications: LMDS/MMDS, point-to-point
GENERAL DESCRIPTION
The AD9146 is a dual, 16-bit, high dynamic range digital-to-
analog converter (DAC) that provides a sample rate of 1000 MSPS
with nominal supplies and 1230 MSPS with increased supplies,
permitting multicarrier generation up to the Nyquist frequency.
The AD9146 TxDAC+® includes features optimized for direct
conversion transmit applications, including complex digital mod-
ulation, and gain and offset compensation. The DAC outputs
are optimized to interface seamlessly with analog quadrature
modulators, such as the ADL537x F-MOD series from Analog
Devices, Inc. A 3-wire serial port interface provides for program-
ming/readback of many internal parameters. Full-scale output
current can be programmed over a range of 8.7 mA to 31.7 mA.
The AD9146 comes in a 48-lead LFCSP.
PRODUCT HIGHLIGHTS
1. Ultralow noise and intermodulation distortion (IMD)
enable high quality synthesis of wideband signals from
baseband to high intermediate frequencies (IF).
2. Proprietary DAC output switching technique enhances
dynamic performance.
3. Current outputs are easily configured for various single-
ended or differential circuit topologies.
4. Compact LVDS digital interface offers reduced width
data bus.
COMPANION PRODUCTS
IQ Modulators: ADL5370, ADL537x family
IQ Modulators with PLL and VCO: ADRF6701, ADRF670x family
Clock Drivers: AD9516, AD951x family
Voltage Regulator Design Tool: ADIsimPower
Additional companion products on the AD9146 product page
COMPLEX BASEBAND
TYPICAL SIGNAL CHAIN
COMPLEX IF
RF
DC
DIGITAL
BASEBAND
PROCESSOR
OFFSET
2/4 AND
GAIN ADJ
OFFSET
2/4 AND
GAIN ADJ
NOTES
1. AQM = ANALOG QUADRATURE MODULATOR.
fIF
SINC–1
I DAC
SINC–1
Q DAC
Figure 1.
LO – fIF
ANTIALIASING
FILTER
AQM PA
LO
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved.
1 page  
AD9146
FUNCTIONAL BLOCK DIAGRAM
Data Sheet
D7P/D7N
D0P/D0N
DCI
FRAME
fDATA/2
FIFO PRE
MOD
HB1
HB2
16
16
10 I OFFSET INV
Q OFFSET SINC
16
16
1.2G
DAC 1 AUX
16-BIT
DAC_CLK
1.2G
DAC 2 AUX
16-BIT
IOUT1P
IOUT1N
IOUT2P
IOUT2N
INTERNAL CLOCK TIMING AND CONTROL LOGIC
PROGRAMMING
REGISTERS
SERIAL
INPUT/OUTPUT
PORT
POWER-ON
RESET
MULTICHIP
SYNCHRONIZATION
SYNC
PLL CONTROL
DAC_CLK
PLL_LOCK
10 10
REF
AND
BIAS
DAC CLK_SEL
0
CLOCK
1 MULTIPLIER
(2× TO 16×)
CLK
RCVR
CLK
RCVR
REFIO
FSADJ
DACCLKP
DACCLKN
REFCLKP
REFCLKN
Figure 2.
Rev. A | Page 4 of 56
5 Page 
AD9146
Data Sheet
Pin No.
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Mnemonic
D0N
DVDD18
TXENABLE
SDIO
SCLK
CS
IRQ
DVDD18
RESET
AVDD33
IOUT2P
IOUT2N
AVDD33
AVSS
REFIO
FSADJ
AVSS
AVDD33
IOUT1N
IOUT1P
AVDD33
EPAD
Description
Data Bit 0 (LSB), Negative.
1.8 V Digital Supply. Supplies power to digital core and digital data ports.
Active High Transmit Path Enable (CMOS). A low level on this pin clamps the DAC outputs to midscale.
Serial Port Data Input/Output (CMOS).
Serial Port Clock Input (CMOS).
Serial Port Chip Select, Active Low (CMOS).
Interrupt Request. Open-drain, active low output. Pull this pin high external to the device.
1.8 V Digital Supply. Supplies power to digital core and digital data ports.
Reset, Active Low (CMOS).
3.3 V Analog Supply.
Q DAC Positive Current Output.
Q DAC Negative Current Output.
3.3 V Analog Supply.
Analog Supply Common.
1.2 V Band Gap Voltage Reference Output. Should be decoupled to AVSS with a 0.1 µF capacitor.
Full-Scale Current Output Adjust. Place a 10 kΩ resistor from this pin to AVSS.
Analog Supply Common.
3.3 V Analog Supply.
I DAC Negative Current Output.
I DAC Positive Current Output.
3.3 V Analog Supply.
The exposed pad (EPAD) must be soldered to the ground plane (AVSS). The EPAD provides an electrical,
thermal, and mechanical connection to the board.
Rev. A | Page 10 of 56
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9146.PDF ] | |
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