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AD9480 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD9480은 전자 산업 및 응용 분야에서
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부품번호 AD9480 기능
기능 250 MSPS 3.3V A/D Converter
제조업체 Analog Devices
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AD9480 데이터시트, 핀배열, 회로
FEATURES
DNL = ± 0.25 LSB
INL = ± 0.26 LSB
Single 3.3 V supply operation (3.0 V to 3.6 V)
Power dissipation of 590 mW at 250 MSPS
1 V p-p analog input range
Internal 1.0 V reference
Single-ended or differential analog inputs
LVDS outputs (ANSI 644 levels)
Power-down mode
Clock duty-cycle stabilizer
APPLICATIONS
Digital oscilloscopes
Instrumentation and measurement
Communications
Point-to-point radios
Predistortion loops
GENERAL DESCRIPTION
The AD9480 is an 8-bit, monolithic analog-to-digital converter
(ADC) optimized for high speed and low power consumption.
Small in size and easy to use, the product operates at a
250 MSPS conversion rate, with excellent linearity and dynamic
performance over its full operating range.
To minimize system cost and power dissipation, the AD9480
includes an internal reference and track-and-hold circuit. The
user only provides a 3.3 V power supply and a differential
encode clock. No external reference or driver components are
required for many applications.
The digital outputs are LVDS (ANSI 644) compatible with an
option of twos complement or binary output format. The
output data bits are provided in parallel fashion along with an
LVDS output clock, which simplifies data capture.
Fabricated on an advanced BiCMOS process, the AD9480 is
available in a 44-lead surface-mount package (TQFP) specified
over the industrial temperature range −40°C to +85°C.
8-Bit, 250 MSPS
3.3 V A/D Converter
AD9480
FUNCTIONAL BLOCK DIAGRAM
VREF SENSE
AGND DrGND DRVDD AVDD
REFERENCE
AD9480
VIN+
VIN–
T&H
8-BIT
ADC
PIPELINE
CORE
8
16
LVDS
D7–D0
(LVDS)
CLK+
CLK–
CLOCK
MGMT
LOGIC
DCO+
DCO-
(LVDS)
PDWN
S1 LVDSBIAS
Figure 1.
PRODUCT HIGHLIGHTS
1. Superior linearity. A DNL of ±0.25 makes the AD9480
suitable for instrumentation and measurement
applications.
2. Power-down mode. A power-down function may be
exercised to bring total consumption down to 15 mW.
3. LVDS outputs (ANSI-644). LVDS outputs simplify timing
and improve noise performance
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2005 Analog Devices, Inc. All rights reserved.




AD9480 pdf, 반도체, 판매, 대치품
AD9480
DC SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = −40°C, TMAX = +85°C, AIN = −1 dBFS, full scale = 1.0 V, internal reference, differential analog and
clock inputs, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error1
Differential Nonlinearity (DNL)
AD9480BSUZ-250
AD9480ASUZ-250
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
Gain Error
Reference
REFERENCE
Internal Reference Voltage
Output Current2
IVREF Input Current3
ISENSE Input Current2
ANALOG INPUTS (VIN+, VIN−)
Differential Input Voltage Range (FS = 1) 4
Common-Mode Voltage
Input Resistance
Input Capacitance
Analog Bandwidth, Full Power
POWER SUPPLY
AVDD
DRVDD
Power Dissipation5
Power-Down Dissipation
IAVDD5
IDRVDD5
Power Supply Rejection Ratio (PSRR)
Temp Test Level
Full VI
25°C I
25°C I
Full VI
Full VI
Full VI
Full V
Full V
Full V
Full VI
25°C IV
25°C I
25°C I
Full V
Full VI
25°C I
Full VI
25°C V
25°C V
Full IV
Full IV
25°C V
25°C V
Full VI
Full VI
25°C V
AD9480-250
Min Typ
Max Unit
8 Bits
Guaranteed
−40
−6.0
+40 mV
+6.0 % FS
−0.5
−0.85
−0.9
±0.28
±0.35
±0.26
+0.5
+0.85
+0.9
LSB
LSB
LSB
30
0.03
±0.025
µV/°C
%FS/°C
mV/°C
0.97 1.0
1.03 V
1.5 mA
100 µA
10 µA
1
1.7 1.9
8.6 10
8.4 10
4
750
V p-p
2.1 V
10.7 kΩ
11.2 kΩ
pF
MHz
3.0 3.3
3.0 3.3
590
15
145
34
−4.2
3.6 V
3.6 V
mW
mW
156 mA
38 mA
mV/V
1 Gain error and gain temperature coefficients are based on the ADC only (with a fixed 1 V external reference and a 1 V p-p differential analog input).
2 Internal reference mode; SENSE = AGND.
3 External reference mode; VREF driven by external 1.0 V reference; SENSE = AVDD.
4 In FS = 1 V, both analog inputs are 500 mV p-p and out of phase with each other.
5 Power dissipation and current measured with rated encode and a dc analog input (outputs static). See Figure 13 for active operation.
Rev. A | Page 3 of 28

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AD9480 전자부품, 판매, 대치품
AD9480
SWITCHING SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V, differential clock input, DCS enabled, unless otherwise noted.
Table 4.
Parameter
CLOCK
Maximum Conversion Rate
Minimum Conversion Rate
Clock Pulse Width High (tEH)
Clock Pulse Width Low (tEL)
OUTPUT PARAMETERS
Valid Time (tV)1
Propagation Delay (tPD)
Rise Time (tR) 20% to 80%
Fall Time (tF) 20% to 80%
DCO Propagation Delay (tCPD)
Data-to-DCO Skew (tPD − tCPD)
Pipeline Latency
APERTURE
Aperture Delay (tA)
Aperture Uncertainty (Jitter)
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
25°C
Test Level
VI
VI
IV
IV
VI
VI
V
V
VI
IV
VI
V
V
1 Valid time is approximately equal to minimum tPD. CLOAD equals 5 pF maximum.
Min
250
1.2
1.2
1.9
1.9
0
AD9480-250
Typ Max
20
2
2
2.8 3.8
0.5
0.5
2.7 3.7
0.1 0.6
8
1.5
0.25
Unit
MSPS
MSPS
ns
ns
ns
ns
ns
ns
ns
ns
Cycles
ns
ps rms
TIMING DIAGRAM
N–1
AIN
CLK+
CLK–
DATA
OUT
DCO+
DCO–
tEH tEL
tCPD
tA
N
N+1
8 CYCLES
1/fS
tPD
N–8
tV
N–7
N+8
N+9
N
Figure 2. Timing Diagram
N+10
N+11
N+1 N+2
Rev. A | Page 6 of 28

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