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PDF AD9484 Data sheet ( Hoja de datos )
| Número de pieza | AD9484 | |
| Descripción | 1.8 V Analog-to-Digital Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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8-Bit, 500 MSPS,
1.8 V Analog-to-Digital Converter
AD9484
FEATURES
SNR = 47 dBFS at fIN up to 250 MHz at 500 MSPS
ENOB of 7.5 bits at fIN up to 250 MHz at 500 MSPS (−1.0 dBFS)
SFDR = 79 dBc at fIN up to 250 MHz at 500 MSPS (−1.0 dBFS)
Integrated input buffer
Excellent linearity
DNL = ±0.1 LSB typical
INL = ±0.1 LSB typical
LVDS at 500 MSPS (ANSI-644 levels)
1 GHz full power analog bandwidth
On-chip reference, no external decoupling required
Low power dissipation
670 mW at 500 MSPS—LVDS SDR output
Programmable (nominal) input voltage range
1.18 V p-p to 1.6 V p-p, 1.5 V p-p nominal
1.8 V analog and digital supply operation
Selectable output data format (offset binary, twos
complement, Gray code)
Clock duty cycle stabilizer
Integrated data capture clock
APPLICATIONS
Wireless and wired broadband communications
Cable reverse path
Communications test equipment
Low cost digital oscilloscopes
Satellite subsystems
Power amplifier linearization
GENERAL DESCRIPTION
The AD9484 is an 8-bit, monolithic, sampling analog-to-digital
converter (ADC) optimized for high performance, low power,
and ease of use. The part operates at up to a 500 MSPS conver-
sion rate and is optimized for outstanding dynamic performance
in wideband carrier and broadband systems. All necessary
functions, including a sample-and-hold and voltage reference,
are included on the chip to provide a complete signal conversion
solution. The VREF pin can be used to monitor the internal
reference or provide an external voltage reference (external
reference mode must be enabled through the SPI port).
The ADC requires a 1.8 V analog voltage supply and a differen-
tial clock for full performance operation. The digital outputs are
LVDS (ANSI-644) compatible and support twos complement,
offset binary format, or Gray code. A data clock output is available
for proper output data timing.
FUNCTIONAL BLOCK DIAGRAM
VREF PWDN
AGND
AVDD
CML
VIN+
VIN–
CLK+
CLK–
REFERENCE
AD9484
TRACK-AND-HOLD
CLOCK
MANAGEMENT
ADC 8
CORE
SERIAL PORT
OUTPUT 8
STAGING
LVDS
SCLK/DFS SDIO CSB
Figure 1.
DRVDD
DRGND
D7± TO D0±
OR+
OR–
DCO+
DCO–
Fabricated on an advanced BiCMOS process, the AD9484 is availa-
ble in a 56-lead LFCSP, and is specified over the industrial
temperature range (−40°C to +85°C). This product is protected
by a U.S. patent.
PRODUCT HIGHLIGHTS
1. High Performance.
Maintains 47 dBFS SNR at 500 MSPS with a 250 MHz input.
2. Ease of Use.
LVDS output data and output clock signal allow interface
to current FPGA technology. The on-chip reference and
sample-and-hold provide flexibility in system design. Use
of a single 1.8 V supply simplifies system power supply design.
3. Serial Port Control.
Standard serial port interface supports various product
functions, such as data formatting, power-down, gain
adjust, and output test pattern generation.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
1 page  
AD9484
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted.
Table 3.
Parameter1
CLOCK INPUTS
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
High Level Input (VIH)
Low Level Input (VIL)
High Level Input Current (IIH)
Low Level Input Current (IIL)
Input Resistance (Differential)
Input Capacitance
LOGIC INPUTS
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Input Current (SDIO, CSB)
Logic 0 Input Current (SDIO, CSB)
Logic 1 Input Current (SCLK, PDWN)
Logic 0 Input Current (SCLK, PDWN)
Input Capacitance
LOGIC OUTPUTS2
VOD Differential Output Voltage
VOS Output Offset Voltage
Output Coding
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Min Typ Max
CMOS/LVDS/LVPECL
0.9
0.2 1.8
−1.8 −0.2
−10 +10
−10 +10
8 10 12
4
0.8 × DRVDD
0.2 × DRVDD
0
−60
50
0
4
247
1.125
454
1.375
Unit
V
V p-p
V p-p
μA
μA
kΩ
pF
V
V
μA
μA
μA
μA
pF
mV
V
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2 LVDS RTERMINATION = 100 Ω.
Rev. A | Page 5 of 24
5 Page 
85 SFDR (dBc), 30.3MHz
80
75 SFDR (dBc), 100.3MHz
70
65
60
55
SNR (dBFS), 30.3MHz
50 SNR (dBFS), 100.3MHz
45
40
50
100 150 200 250 300 350 400 450 500 550
SAMPLE RATE (MSPS)
Figure 10. SNR/SFDR vs. Sample Rate; 30.3 MHz, 100.3 MHz
100
90 SFDR (dBFS)
80
70
SFDR (dBc)
60
50 SNR (dBFS)
40
30
SNR (dB)
20
10
0
–50 –45 –40 –35 –30 –25 –20 –15 –10 –5
0
AMPLITUDE (dB)
Figure 11. SNR/SFDR vs. Input Amplitude; 500 MSPS,140.3 MHz
0.10
0.08
0.06
0.04
0.02
0
–0.02
–0.04
–0.06
–0.08
–0.10
0
64 128
OUTPUT CODE
Figure 12. INL, 500 MSPS
192
256
AD9484
0.10
0.08
0.06
0.04
0.02
0
–0.02
–0.04
–0.06
–0.08
–0.10
0
64 128 192
OUTPUT CODE
Figure 13. DNL, 500 MSPS
256
4.0
0.29 LSB rms
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
N–3
N–2
N–1
N N+1
BINS
N+2
N+3
Figure 14. Grounded Input Histogram, 500 MSPS
0
–10
500MSPS
119.5MHz AT –7.0dBFS
–20
122.5MHz AT –7.0dBFS
SFDR: 77dBc
–30
–40
–50
–60
–70
–80
–90
–100
0
20 40 60 80 100 120 140 160 180 200 220 240
FREQUENCY (MHz)
Figure 15. 64k Point, Two-Tone FFT; 500 MSPS,
119.2 MHz, 122.5 MHz
Rev. A | Page 11 of 24
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet AD9484.PDF ] | |
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