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Analog Devices에서 제조한 전자 부품 AD9838은 전자 산업 및 응용 분야에서
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AD9838 데이터시트, 핀배열, 회로
www.DataSheet4U.net
11 mW Power, 2.3 V to 5.5 V,
Complete DDS
AD9838
FEATURES
2.3 V to 5.5 V power supply
MCLK speed: 16 MHz (B grade), 5 MHz (A grade)
Output frequency up to 8 MHz
Sinusoidal and triangular outputs
On-board comparator
3-wire SPI interface
Extended temperature range: −40°C to +125°C
Power-down option
11 mW power consumption at 2.3 V
20-lead LFCSP
APPLICATIONS
Frequency stimulus/waveform generation
Frequency phase tuning and modulation
Low power RF/communications systems
Liquid and gas flow measurement
Sensory applications: proximity, motion, and defect detection
Test and medical equipment
GENERAL DESCRIPTION
The AD9838 is a low power DDS device capable of producing high
performance sine and triangular outputs. It also has an on-board
comparator that allows a square wave to be produced for clock
generation. Consuming only 11 mW of power at 2.3 V, the
AD9838 is an ideal candidate for power-sensitive applications.
Capability for phase modulation and frequency modulation is
provided. The frequency registers are 28 bits wide: with a 16 MHz
clock rate, resolution of 0.06 Hz can be achieved; with a 5 MHz
clock rate, the AD9838 can be tuned to 0.02 Hz resolution.
Frequency and phase modulation are configured by loading
registers through the serial interface and by toggling the registers
using software or the FSELECT and PSELECT pins, respectively.
The AD9838 is written to via a 3-wire serial interface. This serial
interface operates at clock rates up to 40 MHz and is compatible
with DSP and microcontroller standards.
The device operates with a power supply from 2.3 V to 5.5 V. The
analog and digital sections are independent and can be run from
different power supplies; for example, AVDD can equal 5 V with
DVDD equal to 3 V.
The AD9838 has a power-down pin (SLEEP) that allows external
control of the power-down mode. Sections of the device that are
not being used can be powered down to minimize current con-
sumption. For example, the DAC can be powered down when
a clock output is being generated.
The AD9838 is available in a 20-lead LFCSP_WQ package.
AVDD AGND DGND
FUNCTIONAL BLOCK DIAGRAM
DVDD CAP/2.5V
REFOUT FSADJUST
MCLK
FSELECT
28-BIT FREQ0
REG
28-BIT FREQ1
REG
REGULATOR
VCC
2.5V
ON-BOARD
REFERENCE
FULL-SCALE
CONTROL
MUX
PHASE
ACCUMULATOR
(28-BIT)
12
Σ
SIN
ROM
MUX
10-BIT
DAC
12-BIT PHASE0 REG
12-BIT PHASE1 REG
MUX
MUX
DIVIDE
BY 2
MSB
COMP
IOUT
IOUTB
16-BIT CONTROL
REGISTER
MUX
SIGN BIT OUT
SERIAL INTERFACE
AND
CONTROL LOGIC
COMPARATOR
VIN
AD9838
FSYNC SCLK SDATA
PSELECT
SLEEP RESET
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.




AD9838 pdf, 반도체, 판매, 대치품
AD9838
Parameter1
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINH/IINL
Input Capacitance, CIN
POWER SUPPLIES
AVDD
DVDD
IAA 5
IDD5
A Grade
B Grade
IAA + IDD5
A Grade
B Grade
Low Power Sleep Mode
A Grade
B Grade
Min Typ Max Unit
1.7
2.0
2.8
3
V
V
V
0.6 V
0.7 V
0.8 V
10 μA
pF
2.3 5.5 V
2.3 5.5 V
3.7 5
mA
0.9 2
mA
1.2 2.4 mA
4.6 7
mA
4.9 7.4 mA
0.4 mA
0.4 mA
1 Operating temperature range is −40°C to +125°C; typical specifications are at 25°C.
2 For compliance with the specified load of 200 Ω, IOUT full scale should not exceed 4 mA.
3 Guaranteed by design.
4 Applies when REFOUT is sourcing current. The impedance is higher when REFOUT is sinking current.
5 Measured with the digital inputs static and equal to 0 V or DVDD.
Test Conditions/Comments
2.3 V to 2.7 V power supply
2.7 V to 3.6 V power supply
4.5 V to 5.5 V power supply
2.3 V to 2.7 V power supply
2.7 V to 3.6 V power supply
4.5 V to 5.5 V power supply
fMCLK = 16 MHz, fOUT = fMCLK/4096
IDD code dependent; see Figure 7
See Figure 6
DAC powered down; see Table 17
Rev. A | Page 4 of 32

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AD9838 전자부품, 판매, 대치품
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD9838
AVDD 1
DVDD 2
CAP/2.5V 3
DGND 4
MCLK 5
AD9838
TOP
VIEW
(Not to Scale)
15 AGND
14 VIN
13 SIGN BIT OUT
12 FSYNC
11 SCLK
NOTES
1. CONNECT EXPOSED PAD TO GROUND.
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1
AVDD
Positive Power Supply for the Analog Section. AVDD can have a value from 2.3 V to 5.5 V. A 0.1 μF decoupling
capacitor should be connected between AVDD and AGND.
2
DVDD
Positive Power Supply for the Digital Section. DVDD can have a value from 2.3 V to 5.5 V. A 0.1 μF decoupling
capacitor should be connected between DVDD and DGND.
3
CAP/2.5V
The digital circuitry operates from a 2.5 V power supply. This 2.5 V is generated from DVDD using an on-board
regulator when DVDD exceeds 2.7 V. The regulator requires a decoupling capacitor of 100 nF typical, which is
connected from CAP/2.5V to DGND. If DVDD is less than or equal to 2.7 V, CAP/2.5V should be shorted to DVDD.
4
DGND
Digital Ground.
5
MCLK
Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK. The
output frequency accuracy and phase noise are determined by this clock.
6
FSELECT
Frequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is used in the phase
accumulator. The frequency register to be used can be selected using the FSELECT pin or the FSEL bit. When
the FSEL bit is used to select the frequency register, the FSELECT pin should be tied to CMOS high or low.
7
PSELECT
Phase Select Input. PSELECT controls which phase register, PHASE0 or PHASE1, is added to the phase accumulator
output. The phase register to be used can be selected using the PSELECT pin or the PSEL bit. When the PSEL bit
is used to select the phase register, the PSELECT pin should be tied to CMOS high or low.
8
RESET
Active High Digital Input. This pin resets the appropriate internal registers to 0 (this corresponds to an analog
output of midscale). RESET does not affect any of the addressable registers.
9
SLEEP
Active High Digital Input. When this pin is high, the DAC is powered down. This pin has the same function as
the SLEEP12 control bit.
10
SDATA
Serial Data Input. The 16-bit serial data-word is applied to this input.
11 SCLK Serial Clock Input. Data is clocked into the AD9838 on each falling edge of SCLK.
12
FSYNC
Active Low Control Input. FSYNC is the frame synchronization signal for the input data. When FSYNC is taken
low, the internal logic is informed that a new word is being loaded into the device.
13 SIGN BIT OUT Logic Output. The comparator output is available on this pin or, alternatively, the MSB from the NCO can be
output on this pin. Setting the OPBITEN bit in the control register to 1 enables this output pin. The SIGN/PIB bit
determines whether the comparator output or the MSB from the NCO is output on this pin.
14 VIN
Input to Comparator. The comparator can be used to generate a square wave from the sinusoidal DAC output.
The DAC output should be filtered appropriately before it is applied to the comparator to reduce jitter. When
the OPBITEN and SIGN/PIB bits in the control register are set to 1, the comparator input is connected to VIN.
15
AGND
Analog Ground.
16, 17
IOUT,
IOUTB
Current Output. This is a high impedance current source. A load resistor of nominally 200 Ω should be connected
between IOUT and AGND. IOUTB should be tied to AGND through an external load resistor of 200 Ω, but it can
be tied directly to AGND. A 20 pF capacitor to AGND is also recommended to prevent clock feedthrough.
Rev. A | Page 7 of 32

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