Datasheet.kr   

ADRF6603 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 ADRF6603은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 ADRF6603 자료 제공

부품번호 ADRF6603 기능
기능 1100 MHz to 3200 MHz Rx Mixer
제조업체 Analog Devices
로고 Analog Devices 로고


ADRF6603 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




전체 30 페이지수

미리보기를 사용할 수 없습니다

ADRF6603 데이터시트, 핀배열, 회로
Data Sheet
1100 MHz to 3200 MHz Rx Mixer with
Integrated Fractional-N PLL and VCO
ADRF6603
FEATURES
Rx mixer with integrated fractional-N PLL
RF input frequency range: 1100 MHz to 3200 MHz
Internal LO frequency range: 2100 MHz to 2600 MHz
Input P1dB: 14.8 dBm
Input IP3: 28.5 dBm
IIP3 optimization via external pin
SSB noise figure
IP3SET pin open: 14.3 dB
IP3SET pin at 3.3 V: 15.6 dB
Voltage conversion gain: 6.7 dB
Matched 200 Ω IF output impedance
IF 3 dB bandwidth: 500 MHz
Programmable via 3-wire SPI interface
40-lead, 6 mm × 6 mm LFCSP
APPLICATIONS
Cellular base stations
GENERAL DESCRIPTION
The ADRF6603 is a high dynamic range active mixer with
integrated phase-locked loop (PLL) and voltage controlled
oscillator (VCO). The PLL/synthesizer uses a fractional-N
PLL to generate a fLO input to the mixer. The reference input
can be divided or multiplied and then applied to the PLL phase
frequency detector (PFD).
The PLL can support input reference frequencies from 12 MHz
to 160 MHz. The PFD output controls a charge pump whose
output drives an off-chip loop filter.
The loop filter output is then applied to an integrated VCO. The
VCO output at 2 × fLO is applied to an LO divider, as well as to a
programmable PLL divider. The programmable PLL divider is
controlled by a sigma-delta (Σ-Δ) modulator (SDM). The modulus
of the SDM can be programmed from 1 to 2047.
The active mixer converts the single-ended 50 Ω RF input to
a 200 Ω differential IF output. The IF output can operate up
to 500 MHz.
The ADRF6603 is fabricated using an advanced silicon-germanium
BiCMOS process. It is available in a 40-lead, RoHS-compliant,
6 mm × 6 mm LFCSP with an exposed paddle. Performance is
specified over the −40°C to +85°C temperature range.
Table 1.
Part No.
ADRF6601
ADRF6602
ADRF6603
ADRF6604
Internal LO
Range
750 MHz
1160 MHz
1550 MHz
2150 MHz
2100 MHz
2600 MHz
2500 MHz
2900 MHz
±3 dB RFIN
Balun Range
300 MHz
2500 MHz
1000 MHz
3100 MHz
1100 MHz
3200 MHz
1200 MHz
3600 MHz
±1 dB RFIN
Balun Range
450 MHz
1600 MHz
1350 MHz
2750 MHz
1450 MHz
2850 MHz
1600 MHz
3200 MHz
LODRV_EN 36
LON 37
LOP 38
PLL_EN 16
DATA 12
CLK 13
LE 14
REF_IN 6
MUXOUT 8
FUNCTIONAL BLOCK DIAGRAM
VCC1
1
VCC2 VCC_LO VCC_MIX VCC_V2I VCC_LO
10 17 22 27 34
NC NC
32 33
ADRF6603
INTERNAL LO RANGE
2100MHz TO 2600MHz
3.3V
LDO
2 DECL3P3
BUFFER
2.5V
LDO
9 DECL2P5
SPI
INTERFACE
×2
MUX
÷2
÷4
FRACTION
REG
MODULUS
INTEGER
REG
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
N COUNTER
21 TO 123
TEMP
SENSOR
+
PHASE
FREQUENCY
DETECTOR
BUFFER
PRESCALER
÷2
CHARGE PUMP
250µA,
500µA (DEFAULT),
750µA,
1000µA
2:1
MUX
DIV
BY
2, 1
VCO
CORE
VCO
LDO
40 DECLVCO
26 RFIN
29 IP3SET
4 7 11 15 20 21 23 24 25 28 30 31 35
GND
5
RSET
3 39
18 19
CP VTUNE IFP IFN
Figure 1.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2010–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




ADRF6603 pdf, 반도체, 판매, 대치품
ADRF6603
Data Sheet
SYNTHESIZER/PLL SPECIFICATIONS
VS = 5 V; ambient temperature (TA) = 25°C; fREF = 153.6 MHz; fREF power = 4 dBm; fPFD = 38.4 MHz; high-side LO injection;
fIF = 140 MHz; IIP3 optimized using CDAC (0x1) and IP3SET (3.3 V), unless otherwise noted.
Table 3.
Parameter
SYNTHESIZER SPECIFICATIONS
Frequency Range
Figure of Merit1
Reference Spurs
PHASE NOISE
Integrated Phase Noise
PFD Frequency
REFERENCE CHARACTERISTICS
REF_IN Input Frequency
REF_IN Input Capacitance
MUXOUT Output Level
MUXOUT Duty Cycle
CHARGE PUMP
Pump Current
Output Compliance Range
Test Conditions/Comments
Synthesizer specifications referenced to 1× LO
Internally generated LO
PREF_IN = 0 dBm
fPFD = 38.4 MHz
fPFD/4
fPFD
>fPFD
fLO = 2100 MHz to 2600 MHz, fPFD = 38.4 MHz
1 kHz to 10 kHz offset
100 kHz offset
500 kHz offset
1 MHz offset
5 MHz offset
10 MHz offset
20 MHz offset
1 kHz to 40 MHz integration bandwidth
REF_IN, MUXOUT pins
VOL (lock detect output selected)
VOH (lock detect output selected)
Min
2100
20
12
2.7
Programmable to 250 µA, 500 µA, 750 µA, 1 mA
1
Typ
−222
−107
−82
−85
−88
−99.5
−120
−128
−142
−148
−150
0.42
4
50
500
Max
2600
40
160
0.25
2.8
Unit
MHz
dBc/Hz/Hz
dBc
dBc
dBc
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
°rms
MHz
MHz
pF
V
V
%
µA
V
1 The figure of merit (FOM) is computed as phase noise (dBc/Hz) – 10Log10(fPFD) – 20Log10(fLO/fPFD). The FOM was measured across the full LO range, with fREF = 80 MHz,
and fREF power = 10 dBm (500 V/µs slew rate) with a 40 MHz fPFD. The FOM was computed at 50 kHz offset.
LOGIC INPUT AND POWER SPECIFICATIONS
VS = 5 V; ambient temperature (TA) = 25°C; fREF = 153.6 MHz; fPFD = 38.4 MHz; high-side LO injection; fIF = 140 MHz; IIP3 optimized
using CDAC (0x1) and IP3SET (3.3 V), unless otherwise noted.
Table 4.
Parameter
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINH/IINL
Input Capacitance, CIN
POWER SUPPLIES
Voltage Range
Supply Current
Test Conditions/Comments
CLK, DATA, LE
VCC1, VCC2, VCC_LO, VCC_MIX, and VCC_V2I pins
PLL only
External LO mode (internal PLL disabled, LO output buffer off, IP3SET pin = 3.3 V)
Internal LO mode (internal PLL enabled, IP3SET pin = 3.3 V, LO output buffer on)
Internal LO mode (internal PLL enabled, IP3SET pin = 3.3 V, LO output buffer off)
Power-down mode
Min
1.4
0
4.75
Typ Max Unit
3.3
0.7
0.1
5
V
V
µA
pF
5 5.25 V
97 mA
164 mA
274 mA
261 mA
30 mA
Rev. B | Page 4 of 32

4페이지










ADRF6603 전자부품, 판매, 대치품
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADRF6603
VCC1 1
DECL3P3 2
CP 3
GND 4
RSET 5
REF_IN 6
GND 7
MUXOUT 8
DECL2P5 9
VCC2 10
PIN 1
INDICATOR
ADRF6603
TOP VIEW
(Not to Scale)
30 GND
29 IP3SET
28 GND
27 VCC_V2I
26 RFIN
25 GND
24 GND
23 GND
22 VCC_MIX
21 GND
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PADDLE SHOULD BE SOLDERED TO A
LOW IMPEDANCE GROUND PLANE.
Figure 3. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic Description
1
VCC1
Power Supply for the 3.3 V LDO. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin
should be decoupled with a 100 pF capacitor and a 0.1 µF capacitor located close to the pin.
2 DECL3P3 Decoupling Node for 3.3 V LDO. Connect a 0.1 µF capacitor between this pin and ground.
3 CP Charge Pump Output Pin. Connect to VTUNE through the loop filter.
4, 7, 11, 15, 20, GND
21, 23, 24, 25,
28, 30, 31, 35
Ground. Connect these pins to a low impedance ground plane.
5 RSET Charge Pump Current. The nominal charge pump current can be set to 250 µA, 500 µA, 750 µA, or 1 mA using
Bit DB11 and Bit DB10 in Register 4 and by setting Bit DB18 in Register 4 to 0 (internal reference current). In
this mode, no external RSET is required. If Bit DB18 is set to 1, the four nominal charge pump currents (INOMINAL)
can be externally adjusted according to the following equation:
RSET
=

217.4 × I CP
I NOMINAL

37.8 Ω
6
REF_IN
Reference Input. Nominal input level is 1 V p-p. Input range is 12 MHz to 160 MHz. This pin is internally dc-
biased and should be ac-coupled.
8 MUXOUT Multiplexer Output. This output can be programmed to provide the reference output signal or the lock detect
signal. The output is selected by programming the appropriate register.
9 DECL2P5 Decoupling Node for 2.5 V LDO. Connect a 0.1 µF capacitor between this pin and ground.
10
VCC2
Power Supply for the 2.5 V LDO. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin
should be decoupled with a 100 pF capacitor and a 0.1 µF capacitor located close to the pin.
12
DATA
Serial Data Input. The serial data input is loaded MSB first; the three LSBs are the control bits.
13 CLK Serial Clock Input. The serial clock input is used to clock in the serial data to the registers. The data is latched
into the 24-bit shift register on the CLK rising edge. Maximum clock frequency is 20 MHz.
14 LE Load Enable. When the LE input pin goes high, the data stored in the shift registers is loaded into one of the
eight registers. The relevant latch is selected by the three control bits of the 24-bit word.
16
PLL_EN
PLL Enable. Switch between internal PLL and external LO input. When this pin is logic high, the mixer LO is
automatically switched to the internal PLL and the internal PLL is powered up. When this pin is logic low, the
internal PLL is powered down and the external LO input is routed to the mixer LO inputs. The SPI can also be
used to switch modes.
Rev. B | Page 7 of 32

7페이지


구       성 총 30 페이지수
다운로드[ ADRF6603.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
ADRF6601

300 MHz to 2500 MHz Rx Mixer

Analog Devices
Analog Devices
ADRF6602

1000 MHz to 3100 MHz Rx Mixer

Analog Devices
Analog Devices

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵