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RX621 데이터시트 PDF




Renesas Technology에서 제조한 전자 부품 RX621은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 RX621 자료 제공

부품번호 RX621 기능
기능 (RX62N / RX621) 100 MHz 32-bit RX MCU
제조업체 Renesas Technology
로고 Renesas Technology 로고


RX621 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




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RX621 데이터시트, 핀배열, 회로
Features
Datasheet
RX62N/RX621 Group
RENESAS 32-Bit MCU
R01DS0052EJ0110
Rev.1.10
100 MHz 32-bit RX MCU with FPU, 165 DMIPS, up to 512-Kbyte Flash, Feb 10, 2011
Ethernet, USB 2.0 Full-Speed Host/Function/OTG, CAN, 12-bit ADC, TFT-LCD,
RTC, up to 14 communication channels
Features
32-bit RX CPU Core
Delivers 165 DMIPS at a maximum operating frequency of
100 MHz
Single Precision 32-bit IEEE-754 Floating Point
Accumulator: 32 × 32 to 64-bit result, one instruction
Mult/Divide Unit, 32 × 32 Multiply in one CPU clock for
multiple instructions
Interrupt response in as few as 5 CPU clock cycles
CISC-Harvard Architecture with 5-stage pipeline
Variable length instructions, ultra compact code
Supports the Memory Protection Unit (MPU)
Background JTAG debug plus high-speed trace
Low Power Design and Architecture
2.7V to 3.6V operation from a single supply
480 µA/MHz Run Mode with all peripherals on
Deep Software Standby Mode with RTC
Four low power modes
Main Flash Memory, no Wait-State
100 MHz operation, 10 nsec read cycle
No wait states for read at full CPU speed
256K, 384K, 512K Byte size options
For Instructions or Operands
Programming from USB, SCI, JTAG, user code
Data Flash Memory
Up to 32K Bytes with 30K Erase Cycles
Background Erase/Program does not stall CPU
SRAM, no Wait-State
64K or 96K Byte size options
For Operands or Instructions
Back-up retention in Deep Software Standby Mode
DMA
Four fully programmable internal DMA channels
Two EXDMA channels for external-to-external transfers
Data Transfer Controller (DTC)
Reset and Supply Management
Power-On Reset (POR) monitor/generator
Low Voltage Detect (LVD) with precision setting
System Clocking with Clock Monitoring
External crystal, 8 MHz to 14 MHz to Internal PLL
PLL source to system, USB, and Ethernet
Internal 125 kHz LOCO for IWDT
External crystal, 32 kHz for RTC
Real Time Clock
Full calendar function, BCD format
Two Independent Watchdog Timers
125-kHz LOCO operation
R01DS0052EJ0110 Rev.1.10
wwwF.DeabtaS1h0e,et240U1.n1et
TFLGA85 7×7mm, 0.65mm pitch
TFLGA145 9×9mm, 0.65mm pitch
LFBGA176 13×13mm, 0.8mm pitch
LQFP100 14×14mm, 0.5mm pitch
LQFP144 20×20mm, 0.5mm pitch
Up to 14 Communication Interfaces
(2) USB 2.0 Full-Speed interfaces with PHY
Supports Host/Function/OTG
10 endpoints for types: Control, Interrupt, Bulk, Isochronous
(1) Ethernet MAC 10/100 Mbps, Half or Full Duplex
Supported.
Dedicated DMA with 2-Kbyte transmit and receive FIFOs.
RMII or MII interface to external PHY
(1) CAN ISO11898-1, supports 32 mailboxes
(6) SCI channels: Asynchronous, clock sync, smartcard,
and 9-bit modes
(2) I2C interfaces up to 1M bps, SMBus support
(2) RSPI
External Address Space
Eight CS areas (8 × 16 Mbytes)
128-Mbyte SDRAM area
8-/16-/32-bit bus space selectable for each area
TFT-LCD up to WQVGA resolution
Up to 20 Extended Function Timers
(12) 16-bit MTU2
Input capture, Output Compare, PWM output, phase count
mode
(4) 8-bit TMR
(4) 16-bit CMT
1-MHz ADC units with two combination choices
12-bit × 8 ch. unit with single sample/hold circuit
or (2) 10-bit × 4 ch units each with a sample/hold circuit
AD-converted value addition mode (12-bit A/D converter)
10-bit DAC, 2 channels
Up to 128 GPIO
5V tolerant, Open-Drain, Internal Pull-up
Operation Temp
–40°C to +85°C
Page 1 of 146




RX621 pdf, 반도체, 판매, 대치품
RX62N Group, RX621 Group
1. Overview
Table 1.1 Outline of Specifications (3 / 4)
Classification
Timers
Realtime clock
Communication
function
Module/Function
Programmable pulse
generator
8-bit timers
Compare match
timer
Watchdog timer
Independent
watchdog timer
Ethernet controller
DMA controller for
Ethernet controller
USB 2.0 host/
function module
Serial
communications
interfaces
Description
· (4 bits x 4 groups) x 2 units
· Pulse output with the MTU output as a trigger
· Maximum of 32-bit pulse output possible
· (8 bits x 2 channels) x 2 units
· Select from among seven internal clock signals (PCLK, PCLK/2, PCLK/8, PCLK/32,
PCLK/64, PCLK/1024, PCLK/8192) and one external clock signal
· Capable of output of pulse trains with desired duty cycles or of PWM signals
· The 2 channels of each unit can be cascaded to create a 16-bit timer
· Generation of triggers for A/D converter conversion
· Capable of generating baud-rate clocks for SCI5 and SCI6
· (16 bits x 2 channels) x 2 units
· Select from among four internal clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512)
· 8 bits x 1 channel
· Select from among eight counter-input clock signals (PCLK/4, PCLK/64, PCLK/128,
PCLK/512, PCLK/2048, PCLK/8192, PCLK/32768, PCLK/131072)
· Switchable between watchdog timer mode and interval timer mode
· 14 bits x 1 channel
· Counter-input clock: Dedicated on-chip oscillator
· Clock source: Subclock
· Time/calendar
Interrupt sources: Alarm interrupt, periodic interrupt, and carry interrupt
· Input and output of Ethernet/IEEE 802.3 frames
· Transfer at 10 or 100 Mbps
· Full- and half-duplex modes
· MII (Media Independent Interface) or RMII (Reduced Media Independent Interface) as
defined in IEEE 802.3u
· Detection of Magic PacketsTM* or output of a "wake-on-LAN" signal (WOL)
· Compliance with flow control as defined in IEEE 802.3x standards
Note: * Magic PacketTM is a registered trademark of Advanced Micro Devices, Inc.
· Alleviation of CPU loads by the descriptor control method
· Transmission FIFO: 2 Kbytes; Reception FIFO: 2 Kbytes
· Includes a UDC (USB Device Controller) and transceiver for USB 2.0
· Single port (176-pin products: two ports)
· Compliance with the USB 2.0 specification
· Transfer rate: Full speed (12 Mbps)
· Self-power mode and bus power are selectable
· OTG (On the Go) operation is possible
· Incorporates 2 Kbytes of RAM as a transfer buffer
· 6 channels
· Serial communications modes:
Asynchronous, clock synchronous, and smart-card interface
· Multi-processor communications function
· On-chip baud rate generator allows selection of the desired bit rate
· Choice of LSB-first or MSB-first transfer
· Average transfer rate clock can be input from TMR timers for SCI5 and SCI6
R01DS0052EJ0110 Rev.1.10
Feb 10, 2011
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RX621 전자부품, 판매, 대치품
RX62N Group, RX621 Group
1.2 List of Products
Table 1.3 is a list of products, and Figure 1.1 shows how to read the product part no.
Table 1.3 List of Products
Group
RX62N
RX621
Part No.
Package
R5F562N8BDBG PLBG0176GA-A
R5F562N8BDLE PTLG0145JB-A
R5F562N8BDFB PLQP0144KA-A
R5F562N8BDFP PLQP0100KB-A
R5F562N7BDBG PLBG0176GA-A
R5F562N7BDLE PTLG0145JB-A
R5F562N7BDFB PLQP0144KA-A
R5F562N7BDFP PLQP0100KB-A
R5F562N8ADBG PLBG0176GA-A
R5F562N8ADLE PTLG0145JB-A
R5F562N8ADFB PLQP0144KA-A
R5F562N8ADFP PLQP0100KB-A
R5F562N7ADBG PLBG0176GA-A
R5F562N7ADLE PTLG0145JB-A
R5F562N7ADFB PLQP0144KA-A
R5F562N7ADFP PLQP0100KB-A
R5F56218BDBG PLBG0176GA-A
R5F56218BDLE PTLG0145JB-A
R5F56218BDFB PLQP0144KA-A
R5F56218BDFP PLQP0100KB-A
R5F56218BDLD PTLG0085JA-A
R5F56217BDBG PLBG0176GA-A
R5F56217BDLE PTLG0145JB-A
R5F56217BDFB PLQP0144KA-A
R5F56217BDFP PLQP0100KB-A
R5F56217BDLD PTLG0085JA-A
R5F56216BDBG PLBG0176GA-A
R5F56216BDLE PTLG0145JB-A
R5F56216BDFB PLQP0144KA-A
R5F56216BDFP PLQP0100KB-A
R5F56216BDLD PTLG0085JA-A
ROM Capacity
512 Kbytes
512 Kbytes
512 Kbytes
512 Kbytes
384 Kbytes
384 Kbytes
384 Kbytes
384 Kbytes
512 Kbytes
512 Kbytes
512 Kbytes
512 Kbytes
384 Kbytes
384 Kbytes
384 Kbytes
384 Kbytes
512 Kbytes
512 Kbytes
512 Kbytes
512 Kbytes
512 Kbytes
384 Kbytes
384 Kbytes
384 Kbytes
384 Kbytes
384 Kbytes
256 Kbytes
256 Kbytes
256 Kbytes
256 Kbytes
256 Kbytes
RAM Capacity
96 Kbytes
96 Kbytes
96 Kbytes
96 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
96 Kbytes
96 Kbytes
96 Kbytes
96 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
96 Kbytes
96 Kbytes
96 Kbytes
96 Kbytes
96 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
Data Flash
32 Kbytes
32 Kbytes
32 Kbytes
32 Kbytes
32 Kbytes
32 Kbytes
32 Kbytes
32 Kbytes
32 Kbytes
32 Kbytes
32 Kbytes
32 Kbytes
32 Kbytes
32 Kbytes
32 Kbytes
32 Kbytes
32 Kbytes
32 Kbytes
32 Kbytes
32 Kbytes
32 Kbytes
32 Kbytes
32 Kbytes
32 Kbytes
32 Kbytes
32 Kbytes
32 Kbytes
32 Kbytes
32 Kbytes
32 Kbytes
32 Kbytes
1. Overview
Operating
Frequency
(Max.)
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
R01DS0052EJ0110 Rev.1.10
Feb 10, 2011
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