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부품번호 | KK74HC374A 기능 |
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기능 | Octal 3-State Noninverting D Flip-Flop | ||
제조업체 | KODENSHI KOREA | ||
로고 | |||
TECHNICAL DATA
Octal 3-State
Noninverting D Flip-Flop
High-Performance Silicon-Gate CMOS
KK74HC374A
The KK74HC374A is identical in pinout to the LS/ALS374. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
Data meeting the setup and hold time is clocked to the outputs with
the rising edge of the Clock. The Output Enable input does not affect the
states of the flip-flops, but when Output Enable is high, the outputs are
forced to the high-impedance state; thus, data may be stored even when
the outputs are not enabled.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
KK74HC374AN Plastic
KK74HC374ADW SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
PIN 20=VCC
PIN 10 = GND
www.DataSheet4U.net
FUNCTION TABLE
Output
Enable
L
L
L
Inputs
Clock
L,H,
HX
X = don’t care
Z = high impedance
Output
DQ
HH
LL
X no
change
XZ
1
KK74HC374A
AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input tr=tf=6.0 ns)
Symbol
Parameter
fmax Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
tPLH, tPHL Maximum Propagation Delay, Clock to Q
(Figures 1 and 4)
tPLZ, tPHZ Maximum Propagation Delay, Output Enable to
Q (Figures 2 and 5)
tPZH, tPZL Maximum Propagation Delay, Output Enable to
Q (Figures 2 and 5)
tTLH, tTHL Maximum Output Transition Time, Any Output
(Figures 1 and 4)
CIN
COUT
Maximum Input Capacitance
Maximum Three-State Output Capacitance
(Output in High-Impedance State)
VCC Guaranteed Limit
V 25 °C ≤85°C ≤125°C Unit
to
-55°C
2.0 6.0 5.0 4.0 MHz
4.5 30 24 20
6.0 35 28 24
2.0 125 155 190 ns
4.5 25 31 38
6.0 21 26 32
2.0 150 190 225 ns
4.5 30 38 45
6.0 26 33 38
2.0 150 190 225 ns
4.5 30 38 45
6.0 26 33 38
2.0 75
4.5 15
6.0 13
95 110 ns
19 22
16 19
- 10 10 10 pF
- 15 15 15 pF
Power Dissipation Capacitance (Per Enabled
Output)
CPD Used to determine the no-load dynamic power
consumption: PD=CPDVCC2f+ICCVCC
Typical @25°C,VCC=5.0 V
34
TIMING REQUIREMENTS (CL=50pF,Input tr=tf=6.0 ns)
Symbol
Parameter
VCC
V
tSU Minimum Setup Time, Data to 2.0
Clock (Figure 3)
4.5
6.0
th Minimum Hold Time, Clock 2.0
to Data (Figure 3)
4.5
6.0
tw Minimum Pulse Width, Clock 2.0
(Figure 1)
4.5
6.0
tr, tf Maximum Input Rise and Fall 2.0
Times (Figure 1)
4.5
6.0
Guaranteed Limit
25 °C to
-55°C
≤85°C
≤125°C
50 65 75
10 13 15
9 11 13
555
555
555
60 75 90
12 15 18
10 13 15
1000
500
400
1000
500
400
1000
500
400
pF
Unit
ns
ns
ns
ns
4
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구 성 | 총 6 페이지수 | ||
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구매 문의 | 일반 IC 문의 : 샘플 및 소량 구매 ----------------------------------------------------------------------- IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한 광범위한 전력 반도체를 판매합니다. 전력 반도체 전문업체 상호 : 아이지 인터내셔날 사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ] |
부품번호 | 상세설명 및 기능 | 제조사 |
KK74HC374A | Octal 3-State Noninverting D Flip-Flop | KODENSHI KOREA |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |