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부품번호 | KK74HC74A 기능 |
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기능 | Dual D Flip-Flop | ||
제조업체 | KODENSHI KOREA | ||
로고 | |||
TECHNICAL DATA
Dual D Flip-Flop with Set and Reset
KK74HC74A
The KK74HC74A is identical in pinout to the LS/ALS74. The device inputs
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LS/ALSTTL outputs.
This device consists of two D flip-flops with individual Set, Reset, and
Clock inputs. Information at a D-input is transferred to the corresponding Q
output on the next positive going edge of the clock input. Both Q and Q
outputs are available from each flip-flop. The Set and Reset inputs are
asynchronous.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
KK74HC74AN Plastic
KK74HC74AD SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
PIN 14 =VCC
PIN 7 = GND
www.DataSheet4U.net
FUNCTION TABLE
Inputs
Outputs
Set Reset Clock Data Q Q
LH X XHL
HL X XLH
L L X X H* H*
HH
HHL
HH
LLH
H H L X No Change
H H H X No Change
HH
X No Change
*Both outputs will remain high as long as Set
and Reset are low, but the output states are
unpredictable if Set and Reset go high
simultaneously.
X = don’t care
1
KK74HC74A
AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input tr=tf=6.0 ns)
Symbol
Parameter
VCC Guaranteed Limit
V 25 °C ≤85°C ≤125°C
to
-55°C
fmax Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
2.0 6.0 4.8 4.0
4.5 30 24 20
6.0 35 28 24
tPLH, tPHL Maximum Propagation Delay, Clock to Q or Q
(Figures 1 and 4)
2.0 100 125 150
4.5 20 25 30
6.0 17 21 26
tPLH, tPHL Maximum Propagation Delay, Set or Reset to Q or 2.0 105 130 160
Q (Figures 2 and 4)
4.5 21 26 32
6.0 18 22 27
tTLH, tTHL Maximum Output Transition Time, Any Output
(Figures 1 and 4)
2.0 75
4.5 15
6.0 13
95 110
19 22
16 19
CIN Maximum Input Capacitance
- 10 10 10
Unit
MHz
ns
ns
ns
pF
CPD Power Dissipation Capacitance (Per Flip-Flop)
Used to determine the no-load dynamic power
consumption:
PD=CPDVCC2f+ICCVCC
Typical @25°C,VCC=5.0 V
39
pF
TIMING REQUIREMENTS (CL=50pF,Input tr=tf=6.0 ns)
Symbol
Parameter
VCC
V
tsu Minimum Setup Time, Data to Clock (Figure 3)
2.0
4.5
6.0
th Minimum Hold Time, Clock to Data (Figure 3)
2.0
4.5
6.0
trec Minimum Recovery Time, Set or Reset Inactive to 2.0
Clock (Figure 2)
4.5
6.0
tw Minimum Pulse Width, Clock (Figure 1)
2.0
4.5
6.0
tw Minimum Pulse Width, Set or Reset (Figure 2)
2.0
4.5
6.0
tr, tf Maximum Input Rise and Fall Times (Figure 1)
2.0
4.5
6.0
Guaranteed Limit
25 °C
to-
55°C
≤85°C ≤125°C
80 100 120
16 20 24
14 17 20
3.0 3.0 3.0
3.0 3.0 3.0
3.0 3.0 3.0
8.0 8.0 8.0
8.0 8.0 8.0
8.0 8.0 8.0
60 75 90
12 15 18
10 13 15
60 75 90
12 15 18
10 13 15
1000
500
400
1000
500
400
1000
500
400
Unit
ns
ns
ns
ns
ns
ns
4
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부품번호 | 상세설명 및 기능 | 제조사 |
KK74HC74A | Dual D Flip-Flop | KODENSHI KOREA |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |