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부품번호 | KK74HCT109A 기능 |
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기능 | Dual J-K Flip-Flop | ||
제조업체 | KODENSHI KOREA | ||
로고 | |||
Dual J-K Flip-Flop
with set and Reset
High-Performance Silicon-Gate CMOS
TECHNICAL DATA
KK74HCT109A
The KK74HCT109A is identical in pinout to the LS/ALS109. The
KK74HCT109A may be used as a level converter for interfacing TTL or
NMOS outputs to High Speed CMOS inputs.
This device consists of two J-K flip-flops with individual set, reset, and
clock inputs. Changes at the inputs are reflected at the outputs with the next
low-to-high transition of the clock. Both Q to Q outputs are available from
each flip-flop.
• TTL/NMOS Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 µA
ORDERING INFORMATION
KK74HCT109AN Plastic
KK74HCT109AD SOIC
TA = -55° to 125° C for all packages.
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 16=VCC
PIN 8 = GND
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FUNCTION TABLE
Inputs
Output
Set Reset Clock J K Q Q
LH
X XX H L
HL
LL
X XX L H
X X X H* H*
HH
LL L H
HH
H L Toggle
HH
L H No Change
HH
HH H L
HH
L X X No Change
X = Don’t care
*Both outputs will remain high as long as Set and
Reset are low., but the output states are
unpredictable if Set and Reset go high
simultaneously.
1
KK74HCT109A
AC ELECTRICAL CHARACTERISTICS (VCC=5.5 V ± 10%, CL=50pF,Input tr=tf=6.0 ns)
Symbol
Parameter
fmax
tPLH, tPHL
tPHL
tTLH, tTHL
CIN
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
Maximum Propagation Delay, Clock to Q or Q
(Figures 1 and 4)
Maximum Propagation Delay , Set or Reset to Q
or Q (Figures 2 and 4)
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
Maximum Input Capacitance
Guaranteed Limit
25 °C ≤85 ≤125
to °C °C
-55°C
30 24 20
Unit
MHz
35 44 53 ns
46 58 69 ns
15 19 22 ns
10 10 10 pF
Power Dissipation Capacitance (Per Flip-Flop)
CPD Used to determine the no-load dynamic power
consumption:
PD=CPDVCC2f+ICCVCC+∆ICCVCC
Typical @25°C,VCC=5.0 V
60
pF
TIMING REQUIREMENTS (VCC=5.5 V ± 10%, CL=50pF,Input tr=tf=6.0 ns)
Symbol
Parameter
tSU Minimum Setup Time, J or K
to Clock (Figure 3)
th Minimum Hold Time, Clock
to J or K (Figure 3)
trec Minimum Recovery Time, Set
or Reset Inactive to Clock
(Figure 2)
tw Minimum Pulse Width, Set or
Reset (Figure 2)
tw Minimum Pulse Width,Clock
(Figure 1)
tr, tf Maximum Input Rise and Fall
Times (Figure 1)
Guaranteed Limit
25 °C to
-55°C
≤85°C
≤125°C
20 25 30
555
555
16 20 24
16 20 24
500 500 500
Unit
ns
ns
ns
ns
ns
ns
4
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다운로드 | [ KK74HCT109A.PDF 데이터시트 ] |
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구매 문의 | 일반 IC 문의 : 샘플 및 소량 구매 ----------------------------------------------------------------------- IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한 광범위한 전력 반도체를 판매합니다. 전력 반도체 전문업체 상호 : 아이지 인터내셔날 사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ] |
부품번호 | 상세설명 및 기능 | 제조사 |
KK74HCT109A | Dual J-K Flip-Flop | KODENSHI KOREA |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |