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PDF CYU01M16SCE Data sheet ( Hoja de datos )
| Número de pieza | CYU01M16SCE | |
| Descripción | 16-Mbit (1M x 16) Pseudo Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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PRELIMINARY
CYU01M16SCE
MoBL3™
16-Mbit (1M x 16) Pseudo Static RAM
Features
• Wide voltage range: 2.2V–3.6V
• Access Time: 70 ns
• Ultra-low active power
— Typical active current: 3 mA @ f = 1 MHz
— Typical active current: 18 mA @ f = fmax
• Ultra low standby power
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Offered in a 48-ball BGA Package
• Operating Temperature: –40°C to +85°C
Functional Description[1]
The CYU01M16SCE is a high-performance CMOS Pseudo
Static RAM organized as 1M words by 16 bits that supports an
asynchronous memory interface. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL®) in
Logic Block Diagram
DATA IN DRIVERS
portable applications such as cellular telephones. The device
can be put into standby mode when deselected (CE1 HIGH or
CE2 LOW or both BHE and BLE are HIGH). The input/output
pins (I/O0 through I/O15) are placed in a high-impedance state
when: deselected (CE1 HIGH or CE2 LOW), outputs are
disabled (OE HIGH), both Byte High Enable and Byte Low
Enable are disabled (BHE, BLE HIGH), or during a write
operation (CE1 LOW and CE2 HIGH and WE LOW).
To write to the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A19). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A19).
To read from the device, take Chip Enables (CE1 LOW and
CE2 HIGH) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15.
Refer to the truth table for a complete description of read and
write modes.
A8
A9
A10
A11
A12 1M x 16
A13
A14
RAM Array
A15
A16
A17
A18
A19
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
Power -Down
Circuit
BHE
BLE
BHE
WE
OE
BLE
CE2
CE1
CE2
CE1
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
www.DDaotacSuhmeeetn4Ut #.n:e3t 8-05601 Rev. *D
Revised August 7, 2006
1 page  
PRELIMINARY
CYU01M16SCE
MoBL3™
Switching Characteristics Over the Operating Range[9, 10, 11, 14, 15] (continued)
70 ns
Parameter
Write Cycle[15]
Description
Min.
Max.
Unit
tWC Write Cycle Time
70 40000
ns
tSCE
CE LOW to Write End
60 ns
tAW Address Set-Up to Write End
60 ns
tCD Chip Deselect Time CE1 = HIGH or
CE2 =LOW, BLE/BHE High Pulse Time
15
ns
tHA Address Hold from Write End
0 ns
tSA Address Set-Up to Write Start
0 ns
tPWE
WE Pulse Width
50 ns
tBW BLE/BHE LOW to Write End
60 ns
tSD Data Set-Up to Write End
25 ns
tHD
tHZWE
tLZWE
Data Hold from Write End
WE LOW to High-Z[10, 11, 12]
WE HIGH to Low-Z[10, 11, 12]
0
25
10
ns
ns
ns
Note:
15. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL or CE2 = VIH, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a
write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal
that terminates the write.
Document #: 38-05601 Rev. *D
Page 5 of 11
5 Page 
PRELIMINARY
CYU01M16SCE
MoBL3™
Document History Page
Document Title: CYU01M16SCE MoBL3™ 16-Mbit (1M x 16) Pseudo Static RAM
Document Number: 38-05601
REV.
Orig. of
ECN NO. Issue Date Change
Description of Change
**
342199 See ECN
PCI New Data sheet
*A
386551 See ECN
PCI Changed from Advance to Preliminary
Replaced TBDs with appropriate values
Changed tPC and tPA from 20 to 25 ns
Corrected footnote # 16 as OE = CE1 = VIL and CE2 = VIH
Added separate waveforms for CE1 and CE2 in Read # 2, Page Read and
Write # 1 Timing diagram
*B 422623 See ECN HRT Removed the 55-ns Speed Bin
Changed Isb2 Max value from 60 µA to 70 µA
Added Isb1 to DC Parameters
Added Chip Enable Access Foot Note to AC Parameters
Changed the tCD Min value from 5 ns to 15 ns
Changed the Page Mode Values (tPC and tPAA) from 25 ns to 35 ns
*C 462289 See ECN NXR Revised MPN from CYU01M16SCCU to CYU01M16SCE
Renamed Package Name column with Package Diagram
*D 492939 See ECN NXR Removed Page Mode feature
Document #: 38-05601 Rev. *D
Page 11 of 11
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet CYU01M16SCE.PDF ] | |
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