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부품번호 | CYU01M16SCG 기능 |
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기능 | 16-Mbit (1M x 16) Pseudo Static RAM | ||
제조업체 | Cypress Semiconductor | ||
로고 | |||
PRELIMINARY
CYU01M16SCG
MoBL3™
16-Mbit (1M x 16) Pseudo Static RAM
Features
• Wide voltage range: 2.2V–3.6V
• Access Time: 70 ns
• Ultra-low active power
— Typical active current: 3 mA @ f = 1 MHz
— Typical active current: 18 mA @ f = fmax
• Ultra low standby power
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Offered in a 48-ball BGA Package
• Operating Temperature: –40°C to +85°C
Functional Description[1]
The CYU01M16SCG is a high-performance CMOS Pseudo
Static RAM organized as 1M words by 16 bits that supports an
asynchronous memory interface. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL®) in
Logic Block Diagram
DATA IN DRIVERS
portable applications such as cellular telephones. The device
can be put into standby mode when deselected (CE1 HIGH or
CE2 LOW or both BHE and BLE are HIGH). The input/output
pins (I/O0 through I/O15) are placed in a high-impedance state
when: deselected (CE1 HIGH or CE2 LOW), outputs are
disabled (OE HIGH), both Byte High Enable and Byte Low
Enable are disabled (BHE, BLE HIGH), or during a write
operation (CE1 LOW and CE2 HIGH and WE LOW).
To write to the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A19). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A19).
To read from the device, take Chip Enables (CE1 LOW and
CE2 HIGH) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15.
Refer to the truth table for a complete description of read and
write modes.
A8
A9
A10
A11
A12 1M x 16
A13
A14
RAM Array
A15
A16
A17
A18
A19
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
Power -Down
Circuit
BHE
BLE
BHE
WE
OE
BLE
CE2
CE1
CE2
CE1
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
www.DDaotacSuhmeeetn4Ut #.n:e0t 01-09739 Rev. **
Revised August 7, 2006
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PRELIMINARY
CYU01M16SCG
MoBL3™
AC Test Loads and Waveforms
VCC
OUTPUT
R1
30 pF
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
VCC
GND
10%
90%
90%
10%
R2 Rise Time = 1 V/ns
Fall Time = 1 V/ns
Equivalent to: THEVENIN EQUIVALENT
OUTPUT
RTH
VTH
Parameters
R1
R2
RTH
VTH
3.0V (VCC)
26000
26000
13000
1.50
Unit
Ω
Ω
Ω
V
Switching Characteristics Over the Operating Range[9, 10, 11, 14, 15]
70 ns
Parameter
Description
Min.
Max.
Unit
Read Cycle
tRC[13]
Read Cycle Time
70 40000
ns
tCD Chip Deselect Time CE1 = HIGH or
CE2 =LOW, BLE/BHE High Pulse Time
15
ns
tAA Address to Data Valid
70 ns
tOHA
Data Hold from Address Change
5
ns
tACE
CE LOW to Data Valid
70 ns
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
OE LOW to Data Valid
OE LOW to Low Z[10, 11, 12]
OE HIGH to High Z[10, 11, 12]
CE LOW to Low Z[10, 11, 12]
CE HIGH to High Z[10, 11, 12]
35
5
25
10
25
ns
ns
ns
ns
ns
tDBE
tLZBE
tHZBE
BLE/BHE LOW to Data Valid
BLE/BHE LOW to Low Z[10, 11, 12]
BLE/BHE HIGH to High Z[10, 11, 12]
70
5
25
ns
ns
ns
Notes:
9. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of VCC(typ.)/2, input pulse levels
of 0V to VCC, and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section.
10. At any given temperature and voltage conditions tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any
given device. All low-Z parameters will be measured with a load capacitance of 30 pF (3V).
11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
12. High-Z and Low-Z parameters are characterized and are not 100% tested.
13. If invalid address signals shorter than min.tRC are continuously repeated for 40 µs, the device needs a normal read timing (tRC) or needs to enter standby state
at least once in every 40 µs.
14. In order to achieve 70-ns performance, the read access must be Chip Enable (CE1 or CE2) controlled. That is, the addresses must be stable prior to Chip Enable
going active.
Document #: 001-09739 Rev. **
Page 4 of 11
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4페이지 PRELIMINARY
Switching Waveforms (continued)
Write Cycle 1 (WE Controlled)[15, 12, 16, 19, 20, 21]
tWC
ADDRESS
CE1
CE2
tCD
tSCE
tAW
tSA tPWE
WE
BHE/BLE
tBW
CYU01M16SCG
MoBL3™
tHA
OE
DATA I/O DON’T CARE
tSD
VALID DATA
tHD
tHZOE
Notes:
20. Data I/O is high-impedance if OE > VIH.
21. During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
Document #: 001-09739 Rev. **
Page 7 of 11
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7페이지 | |||
구 성 | 총 11 페이지수 | ||
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부품번호 | 상세설명 및 기능 | 제조사 |
CYU01M16SCCU | 16-Mbit (1M x 16) Pseudo Static RAM | Cypress Semiconductor |
CYU01M16SCE | 16-Mbit (1M x 16) Pseudo Static RAM | Cypress Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |