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PDF CYU01M16ZFC Data sheet ( Hoja de datos )
| Número de pieza | CYU01M16ZFC | |
| Descripción | 16-Mbit (1M x 16) Pseudo Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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PRELIMINARY
CYU01M16ZFC
MoBL3™
16-Mbit (1M x 16) Pseudo Static RAM
Features
• Wide voltage range: 1.7V–1.95V
• Access Time: 70 ns
• Ultra-low active power
— Typical active current: 3 mA @ f = 1 MHz
— Typical active current: 18 mA @ f = fmax
• Ultra low standby power
• 16-word Page Mode
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Deep Sleep Mode
• Offered in a Lead-Free 48-ball BGA Package
• Operating Temperature: –40°C to +85°C
Functional Description[1]
The CYU01M16ZFC is a high-performance CMOS Pseudo
Static RAM organized as 1M words by 16 bits that supports an
asynchronous memory interface. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL®) in
portable applications such as cellular telephones. The device
can be put into standby mode when deselected (CE HIGH or
both BHE and BLE are HIGH). The input/output pins (I/O0
through I/O15) are placed in a high-impedance state when:
deselected (CE HIGH), outputs are disabled (OE HIGH), both
Byte High Enable and Byte Low Enable are disabled (BHE,
BLE HIGH), or during a write operation (CE LOW and WE
LOW).
Writing to the device is accomplished by taking Chip Enable
(CE LOW) and Write Enable (WE) input LOW. If Byte Low
Enable (BLE) is LOW, then data from I/O pins (I/O0 through
I/O7), is written into the location specified on the address pins
(A0 through A19). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A19).
Reading from the device is accomplished by taking Chip
Enables (CE LOW) and Output Enable (OE) LOW while
forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE)
is LOW, then data from the memory location specified by the
address pins will appear on I/O0 to I/O7. If Byte High Enable
(BHE) is LOW, then data from memory will appear on I/O8 to
I/O15. Refer to the truth table for a complete description of read
and write modes.
Deep Sleep Mode is enabled by driving ZZ LOW. See the Truth
Table for a complete description of Read, Write, and Deep
Sleep mode.
Logic Block Diagram
DATA IN DRIVERS
A
A
8
9
A10
A11
A12
A13
1M × 16
RAM Array
A14
AA1156
AAA111987
COLUMN DECODER
I/O0–I/O7
I/O8–I/O15
Power-Down
Circuit
BHE
BLE
BHE
WE
OE
BLE
CE
ZZ
CE
Refresh/Power-down
Circuit
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
www.DDaotacSuhmeeetn4Ut #.n:e3t 8-05604 Rev. *F
Revised January 16, 2006
1 page  
PRELIMINARY
Power-up Characteristics
The initialization sequence is shown in the figure below. Chip
Select (CE) should be HIGH for at least 200 µs after VCC has
reached a stable value. No access must be attempted during
this period of 200 µs.The state of ZZ has to be high (H) for the
duration of power-up.
Stable Power
VCC
ZZ
CE
Tpu
CYU01M16ZFC
MoBL3™
Logic (HIGH)
First Access
Parameter
Tpu
Description
Chip Enable Low After Stable VCC
Min.
200
Typ.
Max.
Unit
µs
Document #: 38-05604 Rev. *F
Page 5 of 14
5 Page 
PRELIMINARY
Switching Waveforms (continued)
Write Cycle 2 (CE Controlled)[15, 16, 19, 22, 23]
ADDRESS
CE
WE
BHE/BLE
t WC
tSA tAW
tSCE
tPWE
tBW
OE
DATA I/O
DON’T CARE
t HZOE
tSD
VALID DATA
CYU01M16ZFC
MoBL3™
tHA
tHD
Write Cycle 3 (WE Controlled, OE LOW)[ 19, 23]
ADDRESS
CE
tWC
tSCE
BHE/BLE
WE
tSA
DATA I/O DON’T CARE
tHZWE
tBW
tAW
tPWE
tSD
VALID DATA
tHA
tHD
tLZWE
Document #: 38-05604 Rev. *F
Page 11 of 14
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet CYU01M16ZFC.PDF ] | |
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