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CY14B064PA 데이터시트 PDF




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부품번호 CY14B064PA 기능
기능 64-Kbit (8 K x 8) SPI nvSRAM
제조업체 Cypress Semiconductor
로고 Cypress Semiconductor 로고


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CY14B064PA 데이터시트, 핀배열, 회로
CY14C064PA
CY14B064PA
CY14E064PA
64-Kbit (8 K × 8) SPI nvSRAM
with Real Time Clock
64-Kbit (8 K × 8) SPI nvSRAM with Real Time Clock
Features
64-Kbit nonvolatile static random access memory (nvSRAM)
Internally organized as 8 K × 8
STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by using SPI
instruction (Software STORE) or HSB pin (Hardware
STORE)
RECALL to SRAM initiated on power-up (Power Up RECALL)
or by SPI instruction (Software RECALL)
Automatic STORE on power-down with a small capacitor
High reliability
Infinite read, write, and RECALL cycles
1 million STORE cycles to QuantumTrap
Data retention: 20 years at 85 °C
Real time clock (RTC)
Full-featured RTC
Watchdog timer
Clock alarm with programmable interrupts
Backup power fail indication
Square wave output with programmable frequency (1 Hz,
512 Hz, 4096 Hz, 32.768 kHz)
Capacitor or battery backup for RTC
Backup current of 0.45 µA (typical)
40 MHz, and 104 MHz High-speed serial peripheral interface
(SPI)
40 MHz clock rate SPI write and read with zero cycle delay
104 MHz clock rate SPI write and read (with special fast read
instructions)
Supports SPI mode 0 (0,0) and mode 3 (1,1)
SPI access to special functions
Nonvolatile STORE/RECALL
8-byte serial number
Manufacturer ID and Product ID
Sleep mode
Logic Block Diagram
VCC VCAP VRTCcap VRTCbat
Write protection
Hardware protection using Write Protect (WP) pin
Software protection using Write Disable instruction
Software block protection for 1/4, 1/2, or entire array
Low power consumption
Average active current of 3 mA at 40 MHz operation
Average standby mode current of 250 µA
Sleep mode current of 8 µA
Industry standard configurations
Operating voltages:
• CY14C064PA : VCC = 2.4 V to 2.6 V
• CY14B064PA : VCC = 2.7 V to 3.6 V
• CY14E064PA : VCC = 4.5 V to 5.5 V
Industrial temperature
16-pin small outline integrated circuit (SOIC) package
Restriction of hazardous substances (RoHS) compliant
Overview
The Cypress CY14X064PA combines a 64 Kbit nvSRAM[1] with
a full-featured RTC in a monolithic integrated circuit with serial
SPI interface. The memory is organized as 8 K words of 8 bits
each. The embedded nonvolatile elements incorporate the
QuantumTrap technology, creating the world’s most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while the QuantumTrap cells provide highly reliable
nonvolatile storage of data. Data transfers from SRAM to the
nonvolatile elements (STORE operation) takes place
automatically at power-down. On power-up, data is restored to
the SRAM from the nonvolatile memory (RECALL operation).
You can also initiate the STORE and RECALL operations
through SPI instruction.
Serial Number
8x8
SI
CS
SCK
WP
SO
Power Control
Block
SLEEP
SPI Control Logic
Write Protection
Instruction decoder
Manufacture ID/
Product ID
RDSN/WRSN/RDID
READ/WRITE
STORE/RECALL/ASENB/ASDISB
Memory
Data &
Address
Control
QuantrumTrap
8Kx8
SRAM
8Kx8
STORE
RECALL
RDRTC/WRTC
WRSR/RDSR/WREN
Status Register
Xin
INT/SQW
Xout
RTC Control Logic
Registers
Counters
Note
1. This device will be referred to as nvSRAM throughout the document.
Cypress Semiconductor Corporation • 198 Champion Court
wwwD.DocautamSheenett4#U: .0n0et1-68249 Rev. *A
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 6, 2011
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CY14B064PA pdf, 반도체, 판매, 대치품
CY14C064PA
CY14B064PA
CY14E064PA
Device Operation
CY14X064PA is a 64-Kbit serial (SPI) nvSRAM memory with
integrated RTC and SPI interface. All the reads and writes to
nvSRAM happen to the SRAM, which gives nvSRAM the unique
capability to handle infinite writes to the memory. The data in
SRAM is secured by a STORE sequence that transfers the data
in parallel to the nonvolatile QuantumTrap cells. A small
capacitor (VCAP) is used to AutoStore the SRAM data in
nonvolatile cells when power goes down providing power-down
data security. The QuantumTrap nonvolatile elements built in the
reliable SONOS technology make nvSRAM the ideal choice for
secure data storage.
In CY14X064PA, the 64-Kbit memory array is organized as 8 K
words × 8 bits. The memory can be accessed through a standard
SPI interface that enables very high clock speeds up to 40 MHz
with zero cycle delay read and write cycles. This nvSRAM chip
also supports 104 MHz SPI access speed with a special
instruction for read operation. CY14X064PA supports SPI
modes 0 and 3 (CPOL, CPHA = 0, 0 and 1, 1) and operates as
SPI slave. The device is enabled using the Chip Select (CS) pin
and accessed through Serial Input (SI), Serial Output (SO), and
Serial Clock (SCK) pins.
CY14X064PA provides the feature for hardware and software
write protection through the WP pin and WRDI instruction.
CY14X064PA also provides mechanisms for block write
protection (1/4, 1/2, or full array) using BP0 and BP1 pins in the
Status Register. Further, the HOLD pin is used to suspend any
serial communication without resetting the serial sequence.
CY14X064PA uses the standard SPI opcodes for memory
access. In addition to the general SPI instructions for read and
write, CY14X064PA provides four special instructions that allow
access to four nvSRAM specific functions: STORE, RECALL,
AutoStore Disable (ASDISB), and AutoStore Enable (ASENB).
The major benefit of nvSRAM over serial EEPROMs is that all
reads and writes to nvSRAM are performed at the speed of SPI
bus with zero cycle delay. Therefore, no wait time is required
after any of the memory accesses. The STORE and RECALL
operations need finite time to complete and all memory accesses
are inhibited during this time. While a STORE or RECALL
operation is in progress, the busy status of the device is indicated
by the Hardware STORE Busy (HSB) pin and also reflected on
the RDY bit of the Status Register.
SRAM Write
All writes to nvSRAM are carried out on the SRAM and do not
use up any endurance cycles of the nonvolatile memory. This
allows you to perform infinite write operations. A write cycle is
performed through the WRITE instruction. The WRITE
instruction is issued through the SI pin of the nvSRAM and
consists of the WRITE opcode, two bytes of address, and one
byte of data. Write to nvSRAM is done at SPI bus speed with zero
cycle delay.
CY14X064PA allows burst mode writes to be performed through
SPI. This enables write operations on consecutive addresses
without issuing a new WRITE instruction. When the last address
in memory is reached in burst mode, the address rolls over to
0x0000 and the device continues to write.
The SPI write cycle sequence is defined in the Memory Access
section of SPI Protocol Description.
SRAM Read
A read cycle is performed at the SPI bus speed. The data is read
out with zero cycle delay after the READ instruction is executed.
READ instruction can be used upto 40 MHz clock speed. The
READ instruction is issued through the SI pin of the nvSRAM and
consists of the READ opcode and two bytes of address. The data
is read out on the SO pin.
Speed higher than 40 MHz (up to 104 MHz) requires
FAST_READ instruction. The FAST_READ instruction is issued
through the SI pin of the nvSRAM and consists of the
FAST_READ opcode, two bytes of address, and one dummy
byte. The data is read out on the SO pin.
CY14X064PA enables burst mode reads to be performed
through SPI. This enables reads on consecutive addresses
without issuing a new READ instruction. When the last address
in memory is reached in burst mode read, the address rolls over
to 0x0000 and the device continues to read.
The SPI read cycle sequence is defined in the Memory Access
section of SPI Protocol Description.
STORE Operation
STORE operation transfers the data from the SRAM to the
nonvolatile QuantumTrap cells. The CY14X064PA STOREs data
to the nonvolatile cells using one of the three STORE operations:
AutoStore, activated on device power-down; Software STORE,
activated by a STORE instruction; and Hardware STORE,
activated by the HSB. During the STORE cycle, an erase of the
previous nonvolatile data is first performed, followed by a
program of the nonvolatile elements. After a STORE cycle is
initiated, read/write to CY14X064PA is inhibited until the cycle is
completed.
The HSB signal or the RDY bit in the Status Register can be
monitored by the system to detect if a STORE or Software
RECALL cycle is in progress. The busy status of nvSRAM is
indicated by HSB being pulled LOW or RDY bit being set to ‘1’.
To avoid unnecessary nonvolatile STOREs, AutoStore and
Hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. However, software initiated STORE cycles are
performed regardless of whether a write operation has taken
place.
AutoStore Operation
The AutoStore operation is a unique feature of nvSRAM which
automatically stores the SRAM data to QuantumTrap cells
during power-down. This STORE makes use of an external
capacitor (VCAP) and enables the device to safely STORE the
data in the nonvolatile memory when power goes down.
During normal operation, the device draws current from VCC to
charge the capacitor connected to the VCAP pin. When the
voltage on the VCC pin drops below VSWITCH during power-down,
the device inhibits all memory accesses to nvSRAM and
automatically performs a conditional STORE operation using the
charge from the VCAP capacitor. The AutoStore operation is not
initiated if no write cycle has been performed since last RECALL.
Note If a capacitor is not connected to VCAP pin, AutoStore must
be disabled by issuing the AutoStore Disable instruction
(AutoStore Disable (ASDISB) Instruction on page 17). If
AutoStore is enabled without a capacitor on the VCAP pin, the
device attempts an AutoStore operation without sufficient charge
Document #: 001-68249 Rev. *A
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CY14B064PA 전자부품, 판매, 대치품
CY14C064PA
CY14B064PA
CY14E064PA
Figure 3. System Configuration Using SPI nvSRAM
SCK
MOSI
M IS O
uC ontroller
CS1
HOLD1
CS2
HOLD2
SCK SI
SO
CY14X064PA
CS HOLD
SCK SI
SO
CY14X064PA
CS HOLD
SPI Modes
CY14X064PA device may be driven by a microcontroller with its
SPI peripheral running in either of these two modes:
SPI Mode 0 (CPOL=0, CPHA=0)
SPI Mode 3 (CPOL=1, CPHA=1)
For both these modes, the input data is latched in on the rising
edge of SCK starting from the first rising edge after CS goes
active. If the clock starts from a high state (in mode 3), the first
rising edge after the clock toggles is considered. The output data
is available on the falling edge of SCK.
Figure 4. SPI Mode 0
The two SPI modes are shown in Figure 4 and Figure 5. The
status of clock when the bus master is in standby mode and not
transferring data is:
SCK remains at 0 for Mode 0
SCK remains at 1 for Mode 3
CPOL and CPHA bits must be set in the SPI controller for the
either Mode 0 or Mode 3. CY14X064PA detects the SPI mode
from the status of SCK pin when device is selected by bringing
the CS pin LOW. If SCK pin is LOW when the device is selected,
SPI Mode 0 is assumed and if SCK pin is HIGH, CY14X064PA
works in SPI Mode 3.
Figure 5. SPI Mode 3
CS
SCK
012 345 67
CS
SCK
012 34567
SI 7 6 5 4 3 2 1 0
MSB
LSB
SI 7 6 5 4 3 2 1 0
MSB
LSB
Document #: 001-68249 Rev. *A
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부품번호상세설명 및 기능제조사
CY14B064PA

64-Kbit (8 K x 8) SPI nvSRAM

Cypress Semiconductor
Cypress Semiconductor

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