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부품번호 CY14E512I 기능
기능 512-Kbit (64 K x 8) Serial (I2C) nvSRAM
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CY14E512I 데이터시트, 핀배열, 회로
CY14C512I
CY14B512I, CY14E512I
512-Kbit (64 K × 8) Serial (I2C) nvSRAM
with Real Time Clock
512-Kbit (64 K × 8) Serial (I2C) nvSRAM with Real Time Clock
Features
512-Kbit nonvolatile static random access memory (nvSRAM)
Internally organized as 64 K × 8
STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by using I2C
command (Software STORE) or HSB pin (Hardware STORE)
RECALL to SRAM initiated on power-up (Power-Up
RECALL) or by I2C command (Software RECALL)
Automatic STORE on power-down with a small capacitor
High reliability
Infinite read, write, and RECALL cycles
1 million STORE cycles to QuantumTrap
Data retention: 20 years at 85 C
Real Time Clock (RTC)
Full-featured RTC
Watchdog timer
Clock alarm with programmable interrupts
Backup power fail indication
Square wave output with programmable frequency (1 Hz,
512 Hz, 4096 Hz, 32.768 kHz)
Capacitor or battery backup for RTC
Backup current of 0.45 µA (typical)
High-speed I2C interface
Industry standard 100 kHz and 400 kHz speed
Fast mode Plus 1 MHz speed
High speed 3.4 MHz
Zero cycle delay reads and writes
Write protection
Hardware protection using Write Protect (WP) pin
Software block protection for one-quarter, one-half, or entire
array
I2C access to special functions
Nonvolatile STORE/RECALL
8-byte serial number
Manufacturer ID and Product ID
Sleep mode
Low power consumption
Average active current of 1 mA at 3.4 MHz operation
Average standby mode current of 250 µA
Sleep mode current of 8 µA
Industry standard configurations
Operating voltages:
• CY14C512I : VCC = 2.4 V to 2.6 V
• CY14B512I : VCC = 2.7 V to 3.6 V
• CY14E512I : VCC = 4.5 V to 5.5 V
Industrial temperature
16-pin small outline integrated circuit (SOIC) package
Restriction of hazardous substances (RoHS) compliant
Overview
The Cypress CY14C512I/CY14B512I/CY14E512I combines a
512-Kbit nvSRAM[1] with a full-featured RTC in a monolithic
integrated circuit with serial I2C interface. The memory is
organized as 64 K words of 8 bits each. The embedded
nonvolatile elements incorporate the QuantumTrap technology,
creating the world’s most reliable nonvolatile memory. The
SRAM provides infinite read and write cycles, while the
QuantumTrap cells provide highly reliable nonvolatile storage of
data. Data transfers from SRAM to the nonvolatile elements
(STORE operation) takes place automatically at power-down.
On power-up, data is restored to the SRAM from the nonvolatile
memory (RECALL operation). The STORE and RECALL
operations can also be initiated by the user through I2C
commands.
Logic Block Diagram
VCC VCAP VRTCcap VRTCbat
Power Control
Block
Sleep
Serial Number
8x8
Manufacture ID/
Product ID
Memory Control Register
Command Register
SDA
SCL
A2, A1, A0
WP
2
I C Control Logic
Slave Address
Decoder
Control Registers Slave
Memory Slave
RTC Slave
Memory
Address and Data
Control
Quantrum Trap
64 K x 8
SRAM
64 K x 8
STORE
RECALL
X in
INT/SQW
Xout
RTC Control Logic
Registers
Counters
Note
1. Serial (I2C) nvSRAM will be referred to as nvSRAM throughout the datasheet.
Cypress Semiconductor Corporation • 198 Champion Court
wwwD.DocautamSheenett4#U: .0n0et1-64879 Rev. *B
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 4, 2011
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CY14E512I pdf, 반도체, 판매, 대치품
CY14C512I
CY14B512I, CY14E512I
I2C Interface
I2C bus consists of two lines – serial clock line (SCL) and serial
data line (SDA) – that carry information between multiple devices
on the bus. I2C supports multi-master and multi-slave
configurations. The data is transmitted from the transmitter to the
receiver on the SDA line and is synchronized with the clock SCL
generated by the master.
The SCL and SDA lines are open-drain lines and are pulled up
to VCC using resistors. The choice of a pull-up resistor on the
system depends on the bus capacitance and the intended speed
of operation. The master generates the clock, and all the data
I/Os are transmitted in synchronization with this clock. The
CY14X512I supports up to 3.4 MHz clock speed on SCL line.
Protocol Overview
This device supports only a 7-bit addressable scheme. The
master generates a START condition to initiate the
communication followed by broadcasting a slave select byte.
The slave select byte consists of a 7-bit slave address that the
master intends to communicate with and R/W bit indicating a
read or a write operation. The selected slave responds to this
with an acknowledgement (ACK). After a slave is selected, the
remaining part of the communication takes place between the
master and the selected slave device. The other devices on the
bus ignore the signals on the SDA line until a STOP or Repeated
START condition is detected. The data transfer is done between
the master and the selected slave device through the SDA pin
synchronized with the SCL clock generated by the master.
I2C Protocol – Data Transfer
Each transaction in I2C protocol starts with the master
generating a START condition on the bus, followed by a 7-bit
slave address and eighth bit (R/W) indicating a read (1) or a write
(0) operation. All signals are transmitted on the open-drain SDA
line and are synchronized with the clock on SCL line. Each byte
of data transmitted on the I2C bus is acknowledged by the
receiver by holding the SDA line LOW on the ninth clock pulse.
The request for write by the master is followed by the memory
address and data bytes on the SDA line. The writes can be
performed in burst-mode by sending multiple bytes of data. The
memory address increments automatically after the
receive/transmit of each byte on the falling edge of the ninth
clock cycle. The new address is latched just prior to
sending/receiving the acknowledgment bit. This allows the next
sequential byte to be accessed with no additional addressing. On
reaching the last memory location, the address rolls back to
0x0000 and writes continue. The slave responds to each byte
sent by the master during a write operation with an ACK. A write
sequence can be terminated by the master generating a STOP
or Repeated START condition.
A read request is performed at the current address location
(address next to the last location accessed for read or write). The
memory slave device responds to a read request by transmitting
the data on the current address location to the master. A random
address read may also be performed by first sending a write
request with the intended address of read. The master must
abort the write immediately after the last address byte and issue
a Repeated START or STOP signal to prevent any write
operation. The following read operation starts from this address.
The master acknowledges the receipt of one byte of data by
holding the SDA pin LOW for the ninth clock pulse. The reads
can be terminated by the master sending a no-acknowledge
(NACK) signal on the SDA line after the last data byte. The NACK
signal causes the CY14X512I to release the SDA line and the
master can then generate a STOP or a Repeated START
condition to initiate a new operation.
Figure 2. System Configuration using Serial (I2C) nvSRAM
Vcc
RPmin = (VCC - VOLmax) / IOL
RPmax = tr / Cb
Microcontroller
SDA
SCL
A0 SCL
A1 SDA
A2 WP
Vcc
A0 SCL
A1 SDA
A2 WP
Vcc
A0 SCL
A1 SDA
A2 WP
Document #: 001-64879 Rev. *B
CY14X512I
#0
CY14X512I
#1
CY14X512I
#7
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CY14E512I 전자부품, 판매, 대치품
CY14C512I
CY14B512I, CY14E512I
Slave Device Address
Every slave device on an I2C bus has a device select address.
The first byte after START condition contains the slave device
address with which the master intends to communicate. The
seven MSBs are the device address and the LSB (R/W bit) is
used for indicating Read or Write operation. The CY14X512I
reserves three sets of upper 4 MSBs [7:4] in the slave device
address field for accessing the Memory, RTC Registers, and
Table 1. Slave Device Addressing
Control Registers. The accessing mechanism is described in the
following section.
The nvSRAM product provides three different functionalities:
Memory, RTC Registers and Control Registers functions (such
as serial number and product ID). The three functions of the
device are accessed through different slave device addresses.
The first four most significant bits [7:4] in the device address
register are used to select between the nvSRAM functions.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
Bit 2
Bit 1
Bit 0
nvSRAM
Function Select
CY14X512I Slave Devices
1010
Device select ID
R/W Selects Memory
Memory, 64 K × 8
1101
Device select ID
R/W
Selects RTC
Registers
RTC Registers, 16 × 8
0011
Device select ID
R/W
Selects Control
Registers
Control Registers
- Memory Control Register, 1 × 8
- Serial Number, 8 × 8
- Device ID, 4 × 8
- Command Register, 1 × 8
Memory Slave Device
The nvSRAM device is selected for read/write if the master
issues the slave address as 1010b followed by three bits of
device select. If the slave address sent by the master matches
with the Memory Slave device address, then depending on the
R/W bit of the slave address, the data will be either read from
(R/W = ‘1’) or written to (R/W = ‘0’) the nvSRAM.
The address length for CY14X512I is 16 bits, and thus it requires
two address bytes to map the entire memory address location.
The dedicated two address bytes represent bit A0 to A15.
Figure 7. Memory Slave Device Address
select. Then, depending on the R/W bit of the slave address,
data is either read from (R/W = ‘1’) or written to (R/W = ‘0’) the
RTC Registers. The RTC Registers slave address is followed by
one byte address of RTC Register for read/write operation. The
RTC Registers map is explained in the Table 10.
Figure 8. RTC Registers Slave Device Address
handbook, halfpMagSe B
LSB
1 1 0 1 A2 A1 A0 R/W
Slave ID
Device Select
handbook, halfpMagSe B
10
LSB
1 0 A2 A1 A0 R/W
Slave ID
Device Select
RTC Registers Slave Device
The RTC Registers is selected for read/write if the master issues
the slave address as 1101b followed by three bits of device
Control Registers Slave Device
The Control Registers Slave device includes the serial number,
product ID, Memory Control, and Command Register.
The nvSRAM Control Register Slave device is selected for
read/write if the master issues the slave address as 0011b
followed by three bits of device select. Then, depending on the
R/W bit of the slave address, data is either read from (R/W = ‘1’)
or written to (R/W = ‘0’) the device.
Document #: 001-64879 Rev. *B
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