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PDF H5MS2622JFR Data sheet ( Hoja de datos )
| Número de pieza | H5MS2622JFR | |
| Descripción | 256Mb (8Mx32bit) Mobile DDR SDRAM | |
| Fabricantes | Hynix Semiconductor | |
| Logotipo |  |
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256Mbit MOBILE DDR SDRAM based on 2M x 4Bank x32 I/O
Specification of
256Mb (8Mx32bit) Mobile DDR SDRAM
Memory Cell Array
- Organized as 4banks of 2,097,152 x32
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 1.2 / Apr. 2009
1
1 page  
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Mobile DDR SDRAM 256Mbit (8M x 32bit)
H5MS2622JFR Series
H5MS2532JFR Series
The Hynix H5MS262(53)2JFR series has the special Low Power function of Auto TCSR (Temperature Compensated Self
Refresh) to reduce self refresh current consumption. Since an internal temperature sensor is implemented, it enables
to automatically adjust refresh rate according to temperature without external EMRS command.
Deep Power Down Mode is an additional operating mode for Low Power DDR SDRAM (Mobile DDR SDRAM). This mode
can achieve maximum power reduction by removing power to the memory array within Low Power DDR SDRAM
(Mobile DDR SDRAM). By using this feature, the system can cut off almost all DRAM power without adding the cost of
a power switch and giving up mother-board power-line layout flexibility.
All inputs are LVCMOS compatible. Devices will have a VDD and VDDQ supply of 1.8V (nominal).
The Hynix H5MS262(53)2JFR series is available in the following package:
- 90Ball FBGA [8mm x 13mm, t=1.0mm max]
256Mb Mobile DDR SDRAM ORDERING INFORMATION
Part Number
Clock Frequency
Page Size Org.
Interface
Operating
temperature
Package
H5MS2622JFR-E3M 200MHz(CL3) / 83MHz(CL2)
H5MS2622JFR-J3M 166MHz(CL3) / 83MHz(CL2)
H5MS2622JFR-K3M 133MHz(CL3) / 83MHz(CL2)
2KByte
H5MS2622JFR-L3M 100MHz(CL3) / 66MHz(CL2)
H5MS2532JFR-E3M 200MHz(CL3) / 83MHz(CL2)
4banks x 2Mb
x 32
LVCMOS
Mobile Temp
(-30oC ~ 85oC)
Lead &
Halogen
Free
H5MS2532JFR-J3M 166MHz(CL3) / 83MHz(CL2)
H5MS2532JFR-K3M 133MHz(CL3) / 83MHz(CL2)
1KByte
H5MS2532JFR-L3M 100MHz(CL3) / 66MHz(CL2)
Rev 1.2 / Apr. 2009
5
5 Page 
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Mobile DDR SDRAM 256Mbit (8M x 32bit)
H5MS2622JFR Series
H5MS2532JFR Series
REGISTER DEFINITION I
Mode Register Set (MRS) for Mobile DDR SDRAM
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
00000000
CAS Latency BT Burst Length
Burst Type
A3 Burst Type
0 Sequential
1 Interleave
CAS Latency
A6 A5 A4
000
001
010
011
100
101
110
111
CAS Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
Burst Length
A2 A1 A0
00 0
00 1
01 0
01 1
10 0
10 1
1 10
1 11
Burst Length
A3 = 0
A3=1
Reserved
Reserved
22
44
88
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Rev 1.2 / Apr. 2009
11
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