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PDF H5MS5122DFR Data sheet ( Hoja de datos )
| Número de pieza | H5MS5122DFR | |
| Descripción | Mobile DDR SDRAM 512Mbit | |
| Fabricantes | Hynix Semiconductor | |
| Logotipo |  |
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512Mbit MOBILE DDR SDRAM based on 4M x 4Bank x32 I/O
Specification of
512Mb (16Mx32bit) Mobile DDR SDRAM
Memory Cell Array
- Organized as 4banks of 4,194,304 x32
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 1.2 / Jul. 2008
1
1 page  
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Mobile DDR SDRAM 512Mbit (16M x 32bit)
H5MS5122DFR Series / H5MS5132DFR Series
The Hynix H5MS5122DFR series has the special Low Power function of Auto TCSR (Temperature Compensated Self
Refresh) to reduce self refresh current consumption. Since an internal temperature sensor is implemented, it enables
to automatically adjust refresh rate according to temperature without external EMRS command.
Deep Power Down Mode is an additional operating mode for Low Power DDR SDRAM (Mobile DDR SDRAM). This mode
can achieve maximum power reduction by removing power to the memory array within Low Power DDR SDRAM
(Mobile DDR SDRAM). By using this feature, the system can cut off almost all DRAM power without adding the cost of
a power switch and giving up mother-board power-line layout flexibility.
All inputs are LVCMOS compatible. Devices will have a VDD and VDDQ supply of 1.8V (nominal).
The Hynix H5MS5122DFR series is available in the following package:
- 90Ball FBGA [size: 8mm x 13mm, t=1.0mm max]
512M Mobile DDR SDRAM ORDERING INFORMATION
Part Number
Clock Frequency
Page Size Organization Interface
Package
H5MS5122DFR-E3M 200MHz(CL3) / 83MHz(CL2)
H5MS5122DFR-J3M 166MHz(CL3) / 83MHz(CL2)
H5MS5122DFR-K3M 133MHz(CL3) / 83MHz(CL2)
2KByte
(Normal)
H5MS5122DFR-L3M 100MHz(CL3) / 66MHz(CL2)
H5MS5132DFR-E3M 200MHz(CL3) / 83MHz(CL2)
4banks x 4Mb
x 32
LVCMOS
90 Ball FBGA
Lead & Halogen
Free
H5MS5132DFR-J3M 166MHz(CL3) / 83MHz(CL2)
H5MS5132DFR-K3M 133MHz(CL3) / 83MHz(CL2)
1KByte
(Reduced)
H5MS5132DFR-L3M 100MHz(CL3) / 66MHz(CL2)
Rev 1.2 / Jul. 2008
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5 Page 
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11
Mobile DDR SDRAM 512Mbit (16M x 32bit)
H5MS5122DFR Series / H5MS5132DFR Series
REGISTER DEFINITION II
Extended Mode Register Set (EMRS) for Mobile DDR SDRAM (A13 is used as 1KBytes Reduced page)
BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1 0 0 0 0 0 0 0 DS 0 0 PASR
DS (Drive Strength)
A7 A6 A5
Drive
Strength
0 0 0 Full
0 0 1 Half (Default)
0 1 0 Quarter
0 1 1 Octant
1 0 0 Three-Quarters
Rev 1.2 / Jul. 2008
PASR (Partial Array Self Refresh)
A2 A1 A0 Self Refresh Coverage
0 0 0 All Banks (Default)
0 0 1 Half of Total Bank (BA1=0)
0 1 0 Quarter of Total Bank (BA1=BA0=0)
0 1 1 Reserved
1 0 0 Reserved
1 0 1 One Eighth of Total Bank
(BA1 = BA0 = Row Address MSB=0)
1 1 0 One Sixteenth of Total Bank
(BA1 = BA0 = Row Address 2 MSBs=0)
1 1 1 Reserved
11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet H5MS5122DFR.PDF ] | |
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