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PDF SSM4500GM Data sheet ( Hoja de datos )

Número de pieza SSM4500GM
Descripción N AND P-CHANNEL ENHANCEMENT MODE POWER MOSFET
Fabricantes Silicon Standard 
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SSM4500GM
N AND P-CHANNEL ENHANCEMENT
MODE POWER MOSFET
PRODUCT SUMMARY
Simple Drive Requirement
Low On-resistance
Fast Switching
DESCRIPTION
D2
D2
D1
D1
SO-8
G2
S2
G1
S1
N-CH
P-CH
BVDSS
RDS(ON)
ID
BVDSS
RDS(ON)
ID
The advanced power MOSFETs from Silicon Standard Corp.
provide the designer with the best combination of fast switching,
ruggedized device design, low on-resistance and cost-effectiveness.
The SO-8 package is universally preferred for all commercial-
industrial surface mount applications and suited for low voltage
applications such as DC/DC converters.
G1
Pb-free; RoHS-compliant
D1
G2
S1
20V
30mΩ
6A
-20V
50mΩ
-5A
D2
S2
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
VDS
VGS
ID@TA=25
ID@TA=70
IDM
PD@TA=25
TSTG
TJ
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current3
Continuous Drain Current3
Pulsed Drain Current1
Total Power Dissipation
Linear Derating Factor
Storage Temperature Range
Operating Junction Temperature Range
THERMAL DATA
Symbol
Rthj-a
Parameter
Thermal Resistance Junction-ambient3
Rating
N-channel P-channel
20 -20
±12 ±12
6 -5
4.8 -4
20 -20
2.0
0.016
-55 to 150
-55 to 150
Max.
Value
62.5
Units
V
V
A
A
A
W
W/
Unit
/W
02/13/2008 Rev.1.00
www.SiliconStandard.com
1

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SSM4500GM pdf
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SSM4500GM
N-Channel
6
5
I D =6A
V DS =10V
4
3
2
1
0
0 2 4 6 8 10 12
Q G , Total Gate Charge (nC)
Fig 7. Gate Charge Characteristics
100
10
1
0.1 T A =25 o C
Single Pulse
1ms
10ms
100ms
1s
10s
DC
0.01
0.1
1
V DS (V)
10
100
Fig9. Maximum Safe Operating Area
VDS
90%
10%
VGS
td(on) tr
td(off) tf
f=1.0MHz
1000
Ciss
Coss
100
Crss
10
1 5 9 13 17 21 25 29
V DS (V)
Fig 8. Typical Capacitance Characteristics
1
Duty Factor = 0.5
0.2
0.1
0.1
0.05
0.02
0.01
0.01
Single Pulse
PDM
t
T
Duty factor = t/T
Peak Tj = PDM x Rthja + Ta
Rthja=135oC/W
0.001
0.0001
0.001
0.01 0.1
1
t , Pulse Width (s)
10
100 1000
Fig 10. Effective Transient Thermal Impedance
VG
4.5V
QGS
QG
QGD
Charge
Q
Fig 11. Switching Time Waveform
Fig 12. Gate Charge Waveform
02/13/2008 Rev.1.00
www.SiliconStandard.com
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