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PDF SSM4513M Data sheet ( Hoja de datos )

Número de pieza SSM4513M
Descripción N AND P-CHANNEL ENHANCEMENT MODE POWER MOSFET
Fabricantes Silicon Standard 
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SSM4513M/GM
N AND P-CHANNEL ENHANCEMENT-MODE POWER MOSFETS
Simple drive requirement
Low on-resistance
Fast switching performance
Description
D2
D2
D1
D1
SO-8
G2
S2
G1
S1
N-CH
P-CH
BV DSS
R DS(ON)
ID
BVDSS
RDS(ON)
ID
35V
36m
5.8A
-35V
68m
-4.3A
Advanced Power MOSFETs from Silicon Standard provide the
designer with the best combination of fast switching, ruggedized
device design, low on-resistance and cost-effectiveness.
The SSM4513M is in the SO-8 package, which is widely
preferred for commercial and industrial surface mount applications,
and is well-suited for most low voltage applications.
G1
D1
G2
S1
D2
S2
This device is available with Pb-free lead finish (second-level interconnect) as SSM4513GM.
Absolute Maximum Ratings
Symbol
Parameter
Rating
Units
N-channel P-channel
VDS
VGS
ID @ TA=25°C
ID @ TA=70°C
IDM
PD @ TA=25°C
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current3
Continuous Drain Current3
Pulsed Drain Current1
Total Power Dissipation
Linear Derating Factor
35
±20
5.8
4.7
20
2.0
0.016
-35
±20
-4.3
-3.4
-20
V
V
A
A
A
W
W/°C
TSTG
TJ
Storage Temperature Range
Operating Junction Temperature Range
-55 to 150
-55 to 150
°C
°C
Thermal Data
Symbol
Rthj-a
Parameter
Thermal Resistance Junction-ambient3
Max.
Value
62.5
Unit
°C/W
10/12/2004 Rev.2.01
www.SiliconStandard.com
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SSM4513M pdf
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N-channel
12
ID=5A
V DS =2 8 V
9
SSM4513M/GM
f=1.0MHz
1000
C iss
6 100
C oss
C rss
3
0
0 4 8 12
Q G , Total Gate Charge (nC)
Fig 7. Gate Charge Characteristics
16
100
10
1ms
10ms
1
0.1 T A =25 o C
Single Pulse
100ms
1s
10s
DC
0.01
0.1 1 10
V DS , Drain-to-Source Voltage (V)
100
Fig 9. Maximum Safe Operating Area
10
1 5 9 13 17 21 25 29
V DS , Drain-to-Source Voltage (V)
Fig 8. Typical Capacitance Characteristics
1
Duty factor=0.5
0.2
0.1 0.1
0.05
0.01
0.02
0.01
Single Pulse
PDM
t
T
Duty factor = t/T
Peak Tj = PDM x Rthja + Ta
Rthja =135oC/W
0.001
0.0001
0.001
0.01 0.1
1
t , Pulse Width (s)
10
100 1000
Fig 10. Effective Transient Thermal Impedance
VDS
90%
10%
VGS
td(on) tr
td(off)tf
VG
4.5V
QG
QGS
QGD
Charge
Q
Fig 11. Switching Time Waveform
Fig 12. Gate Charge Waveform
10/12/2004 Rev.2.01
www.SiliconStandard.com
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