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부품번호 QS5917T 기능
기능 LOW SKEW CMOS PLL CLOCK DRIVER
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QS5917T 데이터시트, 핀배열, 회로
www.DataSheet.co.kr
QS5917T
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
LOW SKEW CMOS PLL
CLOCK DRIVER WITH
INTEGRATED LOOP FILTER
INDUSTRIALTEMPERATURERANGE
QS5917T
FEATURES:
• 5V operation
• 2xQ output, Q/2 output, Q output
• Outputs tri-state while RST low
• Internal loop filter RC network
• Low noise TTL level outputs
• < 500ps output skew, Q0-Q4
• PLL disable feature for low frequency testing
• Balanced Drive Outputs ± 24mA
• 132MHz maximum frequency (2xQ output)
• Functional equivalent to Motorola MC88915
• ESD > 2000V
• Latch-up > –300mA
• Available in QSOP and PLCC packages
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION
The QS5917T Clock Driver uses an internal phase locked loop (PLL)
to lock low skew outputs to one of two reference clock inputs. Eight
outputs are available: Q0-Q4, 2xQ, Q/2, Q5. Careful layout and design
insures < 500ps skew between the Q0-Q4, and Q/2 outputs. The QS5917T
includes an internal RC filter which provides excellent jitter characteris-
tics and eliminates the need for external components. In addition, TTL
level outputs reduce clock signal noise. Various combinations of feed-
back and a divide-by-2 in the VCO path allow applications to be custom-
ized for linear VCO operation over a wide range of input SYNC fre-
quencies. The VCO can also be disabled by the PLL_EN signal to allow
low frequency or DC testing. The LOCK output asserts to indicate when
phase lock has been achieved. The QS5917T is designed for use in
high-performance workstations, multi-board computers, networking hardware,
and mainframe systems. Several can be used in parallel or scattered
throughout a system for guaranteed low skew, system-wide clock distri-
bution networks.
For more information on PLL clock driver products, see Application
Note AN-227.
RST
SYNC0
SYNC1
REF_SEL
0
1
LOCK FEEDBACK
PHASE
DETECTOR
LOOP
FILTER
VCO
PLL_EN
FREQ_SEL
01
1 /2 0
RDRDRDRDRDRDRD
Q Q Q Q Q Q QQ
Q/2 Q5 Q4 Q3
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
© 2000 Integrated Device Technology, Inc.
1
Q2
Q1 Q0
2xQ
JULY 2000
DSC-5227/2
Datasheet pdf - http://www.DataSheet4U.net/




QS5917T pdf, 반도체, 판매, 대치품
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QS5917T
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
FREQUENCY SELECTION TABLE
FREQ_SEL
1
1
1
1
0
0
0
0
Output Used for
Feedback
Q/2
Q0 -Q4
Q5
2xQ
Q/2
Q0 -Q4
Q5
2xQ
SYNC (MHz)
(allowable range)
Min. Max
14 F2XQ / 4
28 F2XQ / 2
28 F2XQ / 2
56 F2XQ(1)
7 F2XQ / 8
14 F2XQ / 4
14 F2XQ / 4
28 F2XQ / 2
NOTE:
1. For the –132 speed grade, maximum input frequency is restricted to 100MHz.
Q/2
SYNC
SYNC / 2
– SYNC / 2
SYNC / 4
SYNC
SYNC / 2
– SYNC / 2
SYNC / 4
INDUSTRIALTEMPERATURERANGE
Output Frequency Relationships
Q5 Q Outputs
– SYNC X 2
SYNC X 2
– SYNC
SYNC
SYNC
– SYNC
– SYNC / 2
SYNC / 2
– SYNC X 2
SYNC X 2
– SYNC
SYNC
SYNC
– SYNC
– SYNC / 2
SYNC / 2
2XQ
SYNC X 4
SYNC X 2
– SYNC X 2
SYNC
SYNC X 4
SYNC X 2
– SYNC X 2
SYNC
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: TA = –40°C to +85°C, AVDD/VDD = 5V ± 5%
Symbol
Parameter
Test Conditions
Min. Typ. Max. Unit
VIH Input HIGH Voltage Level
Guaranteed Logic HIGH level
2—— V
VIL Input LOW Voltage Level
VOH Output HIGH Voltage
VOL Output LOW Voltage
IOZ Output Leakage Current
IIN Input Leakage Current
Guaranteed Logic LOW level
VDD = Min., IOH = 24mA (1)
VDD = Min., IOH = 100µA
VDD = Min., IOL = 24mA (1)
VDD = Min., IOL = 100µA
VOUT = VDD or GND, VDD = Max.
VIN = AVDD or GND, AVDD = Max.
— — 0.9 V
2.4 — — V
3— —
— — 0.55 V
— — 0.2
— — ±5 µA
——
±5 µA
NOTE:
1. IOL and IOH are 12mA and –12mA, respectively, for the LOCK output.
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions (1)
ICC Input Power Supply Current per TTL Input HIGH (2) VDD = Max., VIN = 3.4V
ICCD Dynamic Power Supply Current
VDD = Max
NOTES:
1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics.
2. This specification does not apply to the PLL_EN input.
Typ. Max. Unit
0.4 1.5 mA
— 0.4 mA/MHz
4
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QS5917T 전자부품, 판매, 대치품
www.DataSheet.co.kr
QS5917T
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
ORDERING INFORMATION
QS XXXX
XX
Device Type Speed
XX
Package Process
INDUSTRIALTEMPERATURERANGE
Blank Industrial (-40°C to +85°C)
Q Quarter Size Outline Package
J Plastic Leaded Chip Carrier
-70T
-100T
-132T
70MHz Max. Frequency
100MHz Max. Frequency
132MHz Max. Frequency
5917T Low Skew CMOS PLL Clock Driver with Integrated
Loop Filter
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
for Tech Support:
(408) 654-6459
7
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관련 데이터시트

부품번호상세설명 및 기능제조사
QS5917T

LOW SKEW CMOS PLL CLOCK DRIVER

Integrated Device Technology
Integrated Device Technology

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