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기능 QPro Virtex-II 1.5V Radiation Hardened QML Platform FPGAs
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XQR2V6000 데이터시트, 핀배열, 회로
www.DataSheet.co.kr
0
R QPro Virtex-II 1.5V Radiation
Hardened QML Platform FPGAs
DS124 (v1.1) January 8, 2004
0 0 Product Specification
Summary of Radiation Hardened QPro™ Virtex™-II Features
• Industry First Radiation Hardened Platform FPGA
Solution
• Guaranteed total ionizing dose to 200K Rad(si)
• Latch-up immune to LET > 160 MeV-cm2/mg
• SEU in GEO upsets < 1.5E-6 per device day
achievable with recommended redundancy
implementation
• Certified to MIL-PRF-38535 (Qualified Manufacturer
Listing)
• Guaranteed over the full military temperature range
(–55° C to +125° C)
• Ceramic and Plastic Wire-Bond and Flip-Chip Grid
Array Packages
• IP-Immersion Architecture
- Densities from 1M to 6M system gates
- 300+ MHz internal clock speed (Advance Data)
- 622+ Mb/s I/O (Advance Data)
• SelectRAM™ Memory Hierarchy
- 2.5 Mb of dual-port RAM in 18 Kbit block
SelectRAM resources
- Up to 1 Mb of distributed SelectRAM resources
• High-Performance Interfaces to External Memory
- DRAM interfaces
· SDR/DDR SDRAM
· Network FCRAM
· Reduced Latency DRAM
- SRAM interfaces
· SDR/DDR SRAM
· QDR SRAM
- CAM interfaces
• Arithmetic Functions
- Dedicated 18-bit x 18-bit multiplier blocks
- Fast look-ahead carry logic chains
• Flexible Logic Resources
- Up to 67,584 internal registers/latches with Clock
Enable
- Up to 67,584 look-up tables (LUTs) or cascadable
16-bit shift registers
- Wide multiplexers and wide-input function support
- Horizontal cascade chain and sum-of-products
support
- Internal 3-state busing
• High-Performance Clock Management Circuitry
- Up to 12 DCM (Digital Clock Manager) modules
· Precise clock de-skew
· Flexible frequency synthesis
· High-resolution phase shifting
- 16 global clock multiplexer buffers
• Active Interconnect Technology
- Fourth generation segmented routing structure
- Predictable, fast routing delay, independent of
fanout
• SelectIO™-Ultra Technology
- Up to 824 user I/Os
- 19 single-ended and six differential standards
- Programmable sink current (2 mA to 24 mA) per
I/O
- Digitally Controlled Impedance (DCI) I/O: on-chip
termination resistors for single-ended I/O standards
- Differential Signaling
· 622 Mb/s Low-Voltage Differential Signaling I/O
(LVDS) with current mode drivers
· Bus LVDS I/O
· Lightning Data Transport (LDT) I/O with current
driver buffers
· Low-Voltage Positive Emitter-Coupled Logic
(LVPECL) I/O
· Built-in DDR input and output registers
- Proprietary high-performance SelectLink
Technology
· High-bandwidth data path
· Double Data Rate (DDR) link
· Web-based HDL generation methodology
• Supported by Xilinx Foundation Series™ and Alliance
Series™ Development Systems
- Integrated VHDL and Verilog design flows
- Compilation of 10M system gates designs
- Internet Team Design (ITD) tool
• SRAM-Based In-System Configuration
- Fast SelectMAP configuration
- IEEE 1532 support
- Partial reconfiguration
- Unlimited reprogrammability
- Readback capability
• 0.15 µm 8-Layer Metal Process with 0.12 µm
High-Speed Transistors
• 1.5V (VCCINT) Core Power Supply, Dedicated 3.3V
VCCAUX Auxiliary and VCCO I/O Power Supplies
• IEEE 1149.1 Compatible Boundary-Scan Logic Support
© 2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS124 (v1.1) January 8, 2004
Product Specification
www.xilinx.com
1-800-255-7778
1
Datasheet pdf - http://www.DataSheet4U.net/




XQR2V6000 pdf, 반도체, 판매, 대치품
www.DataSheet.co.kr
QPro Virtex-II 1.5V Radiation Hardened QML Platform FPGAs
R
elements. The general routing matrix (GRM) is an array of
routing switches. Each programmable element is tied to a
switch matrix, allowing multiple connections to the general
routing matrix. The overall programmable interconnection is
hierarchical and designed to support high-speed designs.
All programmable elements, including the routing
resources, are controlled by values stored in static memory
cells. These values are loaded in the memory cells during
configuration and can be reloaded to change the functions
of the programmable elements.
Virtex-II Features
This section briefly describes Virtex-II features.
Input/Output Blocks (IOBs)
IOBs are programmable and can be categorized as follows:
• Input block with an optional single-data-rate or
double-data-rate (DDR) register
• Output block with an optional single-data-rate or DDR
register, and an optional 3-state buffer, to be driven
directly or through a single or DDR register
• Bidirectional block (any combination of input and output
configurations)
These registers are either edge-triggered D-type flip-flops
or level-sensitive latches.
IOBs support the following single-ended I/O standards:
• LVTTL, LVCMOS (3.3V, 2.5V, 1.8V, and 1.5V)
• PCI compatible (33 MHz) at 3.3V
• CardBus compliant (33 MHz) at 3.3V
• GTL and GTLP
• HSTL (Class I, II, III, and IV)
• SSTL (3.3V and 2.5V, Class I and II)
• AGP-2X
The digitally controlled impedance (DCI) I/O feature auto-
matically provides on-chip termination for each I/O element.
The IOB elements also support the following differential sig-
naling I/O standards:
• LVDS
• BLVDS (Bus LVDS)
• ULVDS
• LDT
• LVPECL
Two adjacent pads are used for each differential pair. Two or
four IOB blocks connect to one switch matrix to access the
routing resources.
Configurable Logic Blocks (CLBs)
CLB resources include four slices and two 3-state buffers.
Each slice is equivalent and contains:
• Two function generators (F and G)
• Two storage elements
• Arithmetic logic gates
• Large multiplexers
• Wide function capability
• Fast carry look-ahead chain
• Horizontal cascade chain (OR gate)
The function generators F and G are configurable as 4-input
look-up tables (LUTs), as 16-bit shift registers, or as 16-bit
distributed SelectRAM memory.
In addition, the two storage elements are either edge-trig-
gered D-type flip-flops or level-sensitive latches.
Each CLB has internal fast interconnect and connects to a
switch matrix to access general routing resources.
Block SelectRAM Memory
The block SelectRAM memory resources are 18 Kb of
dual-port RAM, programmable from 16K x 1 bit to 512 x 36
bits, in various depth and width configurations. Each port is
totally synchronous and independent, offering three
"read-during-write" modes. Block SelectRAM memory is
cascadable to implement large embedded storage blocks.
Supported memory configurations for dual-port and sin-
gle-port modes are shown in Table 4.
Table 4: Dual-Port And Single-Port Configurations
16K x 1 bit
2K x 9 bits
8K x 2 bits
1K x 18 bits
4K x 4 bits
512 x 36 bits
A multiplier block is associated with each SelectRAM mem-
ory block. The multiplier block is a dedicated 18 x 18-bit
multiplier and is optimized for operations based on the block
SelectRAM content on one port. The 18 x 18 multiplier can
be used independently of the block SelectRAM resource.
Read/multiply/accumulate operations and DSP filter struc-
tures are extremely efficient.
Both the SelectRAM memory and the multiplier resource
are connected to four switch matrices to access the general
routing resources.
Global Clocking
The DCM and global clock multiplexer buffers provide a
complete solution for designing high-speed clocking
schemes.
Up to 12 DCM blocks are available. To generate de-skewed
internal or external clocks, each DCM can be used to elimi-
nate clock distribution delay. The DCM also provides 90-,
180-, and 270-degree phase-shifted versions of its output
clocks. Fine-grained phase shifting offers high-resolution
phase adjustments in increments of 1/256 of the clock
period. Very flexible frequency synthesis provides a clock
output frequency equal to any M/D ratio of the input clock
frequency, where M and D are two integers. For the exact
4
www.xilinx.com
DS124 (v1.1) January 8, 2004
1-800-255-7778
Product Specification
Datasheet pdf - http://www.DataSheet4U.net/

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XQR2V6000 전자부품, 판매, 대치품
www.DataSheet.co.kr
R
QPro Virtex-II 1.5V Radiation Hardened QML Platform FPGAs
Detailed Description
Input/Output Blocks (IOBs)
Virtex-II I/O blocks (IOBs) are provided in groups of two or
four on the perimeter of each device. Each IOB can be used
as an input and/or an output for single-ended I/Os. Two
IOBs can be used as a differential pair. A differential pair is
always connected to the same switch matrix, as shown in
Figure 2.
IOB blocks are designed for high-performance I/Os, sup-
porting 19 single-ended standards, as well as differential
signaling with LVDS, LDT, Bus LVDS, and LVPECL.
Switch
Matrix
IOB
PAD4
IOB
PAD3
IOB
PAD2
IOB
PAD1
Differential Pair
Differential Pair
DS031_30_101600
Figure 2: Virtex-II Input/Output Tile
Note: Differential I/Os must use the same clock.
Supported I/O Standards
Virtex-II IOB blocks feature SelectI/O-Ultra inputs and out-
puts that support a wide variety of I/O signaling standards.
In addition to the internal supply voltage (VCCINT = 1.5V),
output driver supply voltage (VCCO) is dependent on the I/O
standard (see Table 7). An auxiliary supply voltage
(VCCAUX = 3.3 V) is required, regardless of the I/O stan-
dard used. For exact supply voltage absolute maximum rat-
ings, see DC Input and Output Levels.
Table 7: Supported Single-Ended I/O Standards
I/O
Standard
LVTTL
Output
VCCO
3.3
Input
VCCO
3.3
Input
VREF
N/A
Board
Termination
Voltage (VTT)
N/A
LVCMOS33 3.3 3.3 N/A
N/A
LVCMOS25 2.5 2.5 N/A
N/A
LVCMOS18 1.8 1.8 N/A
N/A
LVCMOS15 1.5 1.5 N/A
N/A
PCI33_3
3.3 3.3 N/A
N/A
PCI66_3
3.3 3.3 N/A
N/A
PCI-X
3.3 3.3 N/A
N/A
GTL
Note 1 Note 1 0.8
1.2
GTLP
Note 1 Note 1 1.0
1.5
HSTL_I
1.5 N/A 0.75
0.75
HSTL_II
1.5 N/A 0.75
0.75
HSTL_III
1.5 N/A 0.9
1.5
HSTL_IV
1.5 N/A 0.9
1.5
HSTL_I
1.8 N/A 0.9
0.9
HSTL_II
1.8 N/A 0.9
0.9
HSTL_III
1.8 N/A 1.1
1.8
HSTL_IV
1.8 N/A 1.1
1.8
SSTL2_I
2.5 N/A 1.25
1.25
SSTL2_II
2.5 N/A 1.25
1.25
SSTL3_I
3.3 N/A 1.5
1.5
SSTL3_II
3.3 N/A 1.5
1.5
AGP-2X/AGP 3.3
N/A 1.32
N/A
Notes:
1. VCCO of GTL or GTLP should not be lower than the
termination voltage or the voltage seen at the I/O pad.
DS124 (v1.1) January 8, 2004
Product Specification
www.xilinx.com
1-800-255-7778
7
Datasheet pdf - http://www.DataSheet4U.net/

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XQR2V6000

QPro Virtex-II 1.5V Radiation Hardened QML Platform FPGAs

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