Datasheet.kr   

L24C02B 데이터시트 PDF




LIZE에서 제조한 전자 부품 L24C02B은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 L24C02B 자료 제공

부품번호 L24C02B 기능
기능 (L24Cxx) EEPROM
제조업체 LIZE
로고 LIZE 로고


L24C02B 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.



전체 16 페이지수

미리보기를 사용할 수 없습니다

L24C02B 데이터시트, 핀배열, 회로
Datasheet pdf - http://www.DataSheet4U.net/
www.DataSheet.co.kr Shenzhen LIZE Electronic Technology Co., Ltd
SPECIFICATION
L24C02B/L24C04/L24C08B/L24C16
Version 2.0
reserves the right to change this documentation without prior notice.
Shenzhen LIZE Electronic Technology Co., Ltd
Version: 2.0
Date: 13, Apr. 2010
Page: 1 of 16




L24C02B pdf, 반도체, 판매, 대치품
Datasheet pdf - http://www.DataSheet4U.net/
Tel:86-755-8835 3502/03/04
Website:http://www.lizhiic.com
Fax:86-755-8835 3509
www.DataSheet.co.kr
Pin Descriptions
DEVICE/PAGE ADDRESSES (A2, A1 and A0): The A2, A1 and A0 pins are device address inputs
that are hard wired for the L24C02B. Eight 2K devices may be addressed on a single bus system
(device addressing is discussed in detail under the Device Addressing section).
The L24C04 uses the A2 and A1 inputs for hard wire addressing and a total of four 4K devices may
be addressed on a single bus system. The A0 pin is a no connect and can be connected to ground.
The L24C08B only uses the A2 input for hardwire addressing and a total of two 8K devices may be
addressed on a single bus system. The A0 and A1 pins are no connects and can be connected to
ground.
The L24C16 does not use the device address pins, which limits the number of devices on a single bus
to one. The A0, A1 and A2 pins are no connects and can be connected to ground.
SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-drain
driven and may be wire-ORed with any number of other open-drain or open- collector devices.
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM
device and negative edge clock data out of each device.
WRITE PROTECT (WP): The L24C02B/L24C04/L24C08B/L24C16 has a Write Protect pin that
provides hardware data protection. The Write Protect pin allows normal read/write operations when
connected to ground (GND). When the Write Protect pin is connected to VCC, the write protection
feature is enabled and operates as shown in the following Table 2.
Table 2: Write Protect
WP Pin Status
At VCC
At GND
L24C02B
Full (2K) Array
Part of the Array Protected
L24C04
L24C08B
Full (4K) Array Full (8K) Array
Normal Read/Write Operations
L24C16
Full (16K) Array
Memory Organization
L24C02B, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each, the 2K
requires an 8-bit data word address for random word addressing.
L24C04, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each, the 4K
requires a 9-bit data word address for random word addressing.
L24C08B, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each, the 8K
requires a 10-bit data word address for random word addressing.
L24C16, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 bytes each, the 16K
requires an 11-bit data word address for random word addressing.
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device.
Data on the SDA pin may change only during SCL low time periods (see to Figure 1 on page 5). Data
changes during SCL high periods will indicate a start or stop condition as defined below.
Shenzhen LIZE Electronic Technology Co., Ltd
Version: 2.0
Date: 15, Apr. 2010
Page: 4 of 16

4페이지










L24C02B 전자부품, 판매, 대치품
Datasheet pdf - http://www.DataSheet4U.net/
Tel:86-755-8835 3502/03/04
Website:http://www.lizhiic.com
Fax:86-755-8835 3509
www.DataSheet.co.kr
output a "0" and the addressing device, such as a microcontroller, must terminate the write sequence
with a stop condition. At this time the EEPROM enters an internally timed write cycle, tWR, to the
nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond
until the write is complete (see Figure 5 on page 7).
PAGE WRITE: The 2K EEPROM is capable of an 8-byte page write, and the 4K, 8K and 16K
devices are capable of 16-byte page writes.
A page write is initiated the same as a byte write, but the microcontroller does not send a stop
condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of
the first data word, the microcontroller can transmit up to seven (2K) or fifteen (4K, 8K, 16K) more
data words. The EEPROM will respond with a "0" after each data word received. The microcontroller
must terminate the page write sequence with a stop condition (see Figure 6 on page 8).
The data word address lower three (2K) or four (4K, 8K, 16K) bits are internally incremented
following the receipt of each data word. The higher data word address bits are not incremented,
retaining the memory page row location. When the word address, internally generated, reaches the
page boundary, the following byte is placed at the beginning of the same page. If more than eight (2K)
or sixteen (4K, 8K, 16K) data words are transmitted to the EEPROM, the data word address will "roll
over" and previous data will be overwritten.
ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM
inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition
followed by the device address word. The read/write bit is representative of the operation desired.
Only if the internal write cycle has completed will the EEPROM respond with a "0", allowing the read
or write sequence to continue.
Read Operations
Read operations are initiated the same way as write operations with the exception that the read/write
select bit in the device address word is set to "1". There are three read operations: current address read,
random address read and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the last address
accessed during the last read or write operation, incremented by one. This address stays valid between
operations as long as the chip power is maintained. The address "roll over" during read is from the last
byte of the last memory page to the first byte of the first page. The address "roll over" during write is
from the last byte of the current page to the first byte of the same page.
Once the device address with the read/write select bit set to "1" is clocked in and acknowledged by the
EEPROM, the current address data word is serially clocked out. The microcontroller does not respond
with an input "0" but does generate a following stop condition (see Figure 7 on page 8).
RANDOM READ: A random read requires a "dummy" byte write sequence to load in the data word
address. Once the device address word and data word address are clocked in and acknowledged by the
EEPROM, the microcontroller must generate another start condition. The microcontroller now
initiates a current address read by sending a device address with the read/write select bit high. The
EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller
does not respond with a "0" but does generate a following stop condition (see Figure 8 on page 9).
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random
address read. After the microcontroller receives a data word, it responds with an acknowledge. As
Shenzhen LIZE Electronic Technology Co., Ltd
Version: 2.0
Date: 15, Apr. 2010
Page: 7 of 16

7페이지


구       성 총 16 페이지수
다운로드[ L24C02B.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
L24C02

Serial EEPROM

Link Smart
Link Smart
L24C02B

(L24Cxx) EEPROM

LIZE
LIZE

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵