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D6376 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 D6376
기능 UPD6376
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D6376 데이터시트, 핀배열, 회로
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD6376
AUDIO 2-CHANNEL 16-BIT D/A CONVERTER
The µPD6376 is an audio 2-channel 16-bit D/A converter.
The µPD6376 has low sound quality deterioration by employing the resistor string configuration and 0-point offset,
and low power consumption by using the CMOS process. It operates on a single 5-V power supply, and it is pin-
compatible with the µPD6372 when Pin 1 is low level or open.
FEATURES
• Single 5-V power supply
• CMOS structure
• On-chip output operational amplifier circuit
• On-chip 0-point offset circuit
• Resistor string configuration
• 8 fS (2 ch × 400 kHz) supported
• On-chip 2-channel DAC
• L-R in-phase output
ORDERING INFORMATION
Part Number
µPD6376GS
Package
16-pin plastic SOP (300 mil)
The information in this document is subject to change without notice.
Document No. S12799EJ5V0DS00 (5th edition)
(Previous No. IC-2531)
Date Published December 1997 N
Printed in Japan
The mark shows major revised points.
©
1991
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µPD6376
1. PIN FUNCTIONS
Pin No. Symbol
1 4/8 fS SEL
Name
2 D.GND
Digital GND
3 NC
Non Connection
4 D.VDD
Digital VDD
5 A.GND
Analog GND
6 R.OUT
R-ch OUTPUT
7 A.VDD
Analog VDD
8 A.VDD
Analog VDD
9 R.REF
R-ch Voltage Reference
10 L.REF
L-ch Voltage Reference
11 L.OUT
L-ch OUTPUT
12 A.GND
Analog GND
13 LRCK/WDCK Left/Right Clock
WORD Clock
14 LRSEL/RSI
Left/Right Selection
R-ch Series Input
15 SI/LSI
Series Input
L-ch Series Input
16 CLK
CLOCK
I/O Function
Input
When this pin is Low or leaves Open, L-ch data and R-ch
data is input in time-division from Pin 15.
When this pin is High, L-ch data is input from Pin 15, and
R-ch data is input from Pin 14.
(Pulled down in IC with 100-kresistor)
–– GND pin of logic block
–– Not connected to internal chip
–– Power supply pin to logic block
–– GND pin to analog block
Output Right analog signal output pin
–– Power supply pin to analog block
–– Reference voltage pin. Normally connected to A. GND
through via capacitor to lower impedance
Output Left analog signal output pin
–– GND pin of analog block
Input
When Pin 1 is Low or leaves Open:
Functions as L-R judgment signal input pin.
When Pin 1 is High:
Functions as input data word judgment signal input pin.
Input
When Pin 1 is Low or leaves Open:
Functions as pin to select L-R polarity for LRCK signal.
When LRCK signal is High, set LRSEL pin to Low to input
L-ch data; When LRCK signal is LOW, set LRSEL pin to
High to input L-ch data.
When Pin 1 is High:
Functions as R-ch serial data input pin.
Input
When Pin 1 is Low or Open:
Functions as L-ch and R-ch serial data input pin
alternately.
When Pin 1 is High:
Functions as L-ch serial data input pin.
Input Input pin for read clock of serial input data
4
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µPD6376
2.2 Supplying Clock to CLK only during Sample Data Interval
The analog outputs of the L.OUT and R.OUT pins are updated after the input of 4.5 clocks following data input.
(See 4. ELECTRICAL CHARACTERISTICS, Timing Charts 1 and 2.)
2.2.1 Inputting serial data (Pin 1 Low or Open)
Place the LRCK reverse timing between the falling edge of CLK at LSB input completion (Point A in Figure 2-3)
and the next MSB input start time (Point B in Figure 2-3) (so as to include Points A and B).
Figure 2-3 Timing Chart of Serial Data Input
A
CLK
LSB
SI 16
BA
1-sample data interval
MSB
LSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
B
MSB
1234
LRCK
LRCK reverse interval
LRCK reverse interval
2.2.2 Inputting parallel data (Pin 1 High)
Place the WDCK falling edge timing between the falling edge of CLK at LSB input completion (Point A in Figure
2-4) and the next MSB input start time (Point B in Figure 2-4) (so as to include Points A and B).
Place the WDCK rising edge timing between the third falling edge of CLK from MSB input completion (Point C in
Figure 2-4) and the falling edge of CLK upon LSB input start (Point D in Figure 2-4) (so as to include Points C and
D).
Figure 2-4 Timing Chart of Parallel Data Input
A BC
DA
B
CLK
LSB
LSI 16
LSB
RSI 16
MSB
LSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
MSB
LSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
MSB
12
MSB
12
WDCK
WDCK falling
edge interval
WDCK rising edge interval
WDCK falling
edge interval
7
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