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AR6002 데이터시트 PDF




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부품번호 AR6002 기능
기능 ROCm Single-Chip MAC/BB/Radio
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AR6002 데이터시트, 핀배열, 회로
www.DataSheet.co.kr
Data Sheet
PRELIMINARY
April 2008
AR6002 ROCmTM Single-Chip MAC/BB/Radio for 2.4/5 GHz
Embedded WLAN Applications
General Description
are available in Wafer Level Chip Scale Packages
The Atheros AR6002 is the 2nd generation of the
(WLCSP) or Ball Grid Arrays (BGA) packaging .
WLAN ROCm family. Building on the advanced
AR6002 Features
performance and features of the AR6001 family,
the compact size and low power consumption of
this single chip design make it an ideal vehicle
for adding WLAN to hand-held and other
battery-powered consumer electronic devices.
All-CMOS IEEE 802.11a/b/g or 802.11b/g
single-chip client
Integrated PA, LNA and RF switch
minimizing external component count
Both IEEE 802.11g (2.4 GHz) and 802.11a (5 GHz)
Data rates of 1–54 Mbps for 802.11g, 6-54
standards are supported by the AR6002 family.
Mbps for 802.11a
The AR6002 supports both SDIO 1.1 and GSPI
lhost interfaces.
tiaThe AR6002 family includes a highly integrated,
nfront-end module ((Power Amplifier, Low-Noise
eAmplifier and RF switch), enabling low-cost
fiddesigns with minimal external components. The
nRF performance, data throughput, and power
oconsumption further improve upon the
Cperformance of the AR6001 family. Advanced
sarchitecture and protocol techniques save power
roduring sleep, stand-by and active states.
theFast antenna diversity is also supported,
Aallowing optimal antenna selection on a per-
:packet basis. The AR6002 family supports 2, 3
ryand 4 wire Bluetooth coexistence protocols with
aadvanced algorithms for predicting channel
inusage by the co-located Bluetooth transceiver.
limThe AR6002 family provides multiple peripheral
reinterfaces including UART, SPI, I2C and 18 GPIO
Ppins. All internal clocks are generated from a
Advanced power management to minimize
standby, sleep and active power
Host interface support for SDIO and GSPI
Security support for WPS, WPA2, WPA,
WAPI and protected management frames
Support for 2.4 and 5 GHz operation in all
available bands in all regulatory domains
Full 802.11e QoS support including WMM
and U-APSD
Standard 2, 3 and 4 wire Bluetooth
coexistence handshake support
IEEE 1149.1, JTAG, test access port and
boundary scan
18 fully-programmable GPIO pins
16550-compliant UART
SPI or I2C for EEPROM support
Internally generated low-frequency oscillator
for low-power sleep
single external crystal/oscillator. A variety of
reference clocks are supported which include
19.2, 24, 26, 38.4, 40 and 52 MHz. AR6002 chips
Available in 7 x 7 mm BGA package with 0.5
mm pitch or WLCSP package with 0.4 mm
pitch
HOST
SDIO or GSPI
SDIO
GSPI
Console
EEPROM
LED
Test, ICE
UART
SPI/I2C
GPIO
JTAG
PA
Mailbox A 802.11a/g 802.11a/g 802.11a/g
DMA
H
MAC
BB
Radio
LNA1
B
Bridge
AR6002
I
N
T
E
R
N
A
L
B
U
S
Memory
Controller
RAM
ROM
i-port
d-port
Power, Clock
Management
LNA2
Xtensa
CPU
LF CLK
REF CLK
AR6002 System Block Diagram
LNA2 Input
32 KHz OSC
(optional)
OSC/XTAL
© 2000-2008 by Atheros Communications, Inc. All rights reserved. Atheros™, ROCm™, 5-UP™, Driving the Wireless Future™, Atheros Driven™, Atheros
Turbo Mode™, and the Air is Cleaner at 5-GHz™ are trademarks of Atheros Communications, Inc. The Atheros logo is a registered trademark of
Atheros Communications, Inc. All other trademarks are the property of their respective holders.
Subject to change without notice.
PRELIMINARY: ATHEROS CONFIDENTIAL
1
Datasheet pdf - http://www.DataSheet4U.net/




AR6002 pdf, 반도체, 판매, 대치품
www.DataSheet.co.kr
8 Ordering Information ................. 55
Preliminary: Atheros Confidential
4 • AR6002 MAC/BB/Radio for Embedded WLAN Applications
4 April 2008
Atheros Communications, Inc.
PRELIMINARY: ATHEROS CONFIDENTIAL
Datasheet pdf - http://www.DataSheet4U.net/

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AR6002 전자부품, 판매, 대치품
www.DataSheet.co.kr
automatically de-asserted. The only resets that
stay asserted are given below:
Warm and cold resets to the MAC
Warm reset to the radio (The cold reset gets
automatically de-asserted)
The above resets are deasserted by software.
All AR6002 reset control logic resides in the
RTC block to ensure stable reset generation.
(Use of SYS_RST_L is optional but must be
de-asserted if asserted.) See the Host
Interface chapter for a table listing interface
type options.
3. For SDIO and GSPI interface modes, the
AR6002 enters the HOST_OFF state. The
host then reads interface registers to
determine the type of function that the
AR6002 supports.
1.10.1 CPU Reset
4. When the host is ready to use the WLAN, it
enables the AR6002 by writing to the
The CPU Reset is a bit different from the other
function enable bit which sets the
resets mentioned above. There are four
HOST_PWR_EN signal.
scenarios where the CPU Reset can be asserted:
5. The AR6002 enters the WAKEUP state then
1. It can be driven form the SYS_RST_L pin,
the SOC_ON state and enables the XTENSA
de-assertion of HOST_PWR_EN, or from a
write to an internal register.
tial2. The CPU Reset is also dependent upon the
boot strap signal EJTAG_SEL which is
enlatched from the GPIO_17 pin upon system
fidinitialization. The EJTAG_SEL signal is set
when there is an In-Circuit Emulator (ICE)
nconnected to the chip's JTAG port. In this
Cosituation, it is desirable to hold the CPU in
sreset even after the SYS_RST_L pin has been
rode-asserted and the rest of the chip is
erunning. In this situation, the CPU Reset is
thasserted until GPIO_13 has been set
A(presumably by the ICE).
ry:3. It is also possible to hold the CPU in reset
until the host clears an internal register.
inaThis depends upon the boot-strap signal
CPU_INIT_RST which is latched upon
limsystem initialization from the GPIO_16 pin.
reIf CPU_INIT_RST is set, then the CPU will
be held in reset until the host clears an
Pinternal AR6002 register.
CPU to begin the boot process. Software
configures the AR6002 functions and
interfaces. When the AR6002 is ready to
receive commands from the host, it will set
the function ready bit.
6. The host reads the ready bit and can now
send function commands to the AR6002.
7. The CPU may continue to be held in reset
under some circumstances until its reset is
cleared by an external pin or when the host
clears a register. See section 1.10 above.
8. The MAC cold reset and the MAC/BB
warm reset will continue to stay asserted
until their respective reset registers are
cleared.
1.12 Power Management
The AR6002 provides integrated power
management and control functions and
extremely low power operation for maximum
battery life across all operational states by:
Gating clocks for logic when not needed
4. The CPU can also be reset from the write
that set bit-6 of the RTC_RESET register.
Shutting down unneeded high speed clock
sources
1.11 Reset Sequence
Reducing voltage levels to specific blocks in
some states
After a COLD_RESET event, the AR6002 will
enter the SDIO_OFF state and await an enable
event from the host. The AR6002 CPU will not
execute any instructions until after the host
Reducing Tx and Rx active duty cycles
Lowering CPU frequency when
computational load is reduced
enables the AR6002. The typical AR6002
COLD_RESET sequence is shown below:
1. The host system de-asserts CHIP_PWD_L,
1.12.1 Hardware Power States
AR6002 hardware has six top level hardware
power states managed by the RTC block.
if asserted (use of CHIP_PWD_L is optional,
but must be de-asserted to use the AR6002).
2. SYS_RST_L is de-asserted. The AR6002
Table 1-1 describes the input from the MAC,
CPU, SDIO/MBOX, interrupt logic, and timers
that effect the power states.
latches the input level on GPIO-4 and
Figure 1-1 depicts the state transition diagram.
GPIO-5 to determine the host interface type.
Atheros Communications, Inc.
PRELIMINARY: ATHEROS CONFIDENTIAL
AR6002 MAC/BB/Radio for Embedded WLAN Applications • 7
April 2008 7
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