PDF V58C2256164SC Data sheet ( Hoja de datos )

Número de pieza	V58C2256164SC
Descripción	256 Mbit DDR SDRAM
Fabricantes	ProMOS Technologies
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No Preview Available ! www.DataSheet.co.kr V58C2256(804/404/164)SCI 256 Mbit DDR SDRAM, INDUSTRIAL TEMPERATURE 4 BANKS X 8Mbit X 8 (804) 4 BANKS X 4Mbit X 16 (164) 4 BANKS X 16Mbit X 4 (404) Clock Cycle Time (tCK2) Clock Cycle Time (tCK2.5) Clock Cycle Time (tCK3) System Frequency (fCK max) 5B DDR400 7.5 ns 5ns 5ns 200 MHz 5 DDR400 7.5 ns 6ns 5ns 200 MHz 6 DDR333 7.5 ns 6 ns 6 ns 166 MHz 7 DDR266 7.5ns 7ns 7 ns 143 MHz Features ■ High speed data transfer rates with system frequency up to 200 MHz ■ Data Mask for Write Control ■ Four Banks controlled by BA0 & BA1 ■ Programmable CAS Latency: 2, 2.5, 3 ■ Programmable Wrap Sequence: Sequential or Interleave ■ Programmable Burst Length: 2, 4, 8 for Sequential Type 2, 4, 8 for Interleave Type ■ Automatic and Controlled Precharge Command ■ Power Down Mode ■ Auto Refresh and Self Refresh ■ Refresh Interval: 8192 cycles/64 ms ■ Available in 66-pin 400 mil TSOP or 60 Ball FBGA ■ SSTL-2 Compatible I/Os ■ Double Data Rate (DDR) ■ Bidirectional Data Strobe (DQS) for input and output data, active on both edges ■ On-Chip DLL aligns DQ and DQs transitions with CK transitions ■ Differential clock inputs CK and CK ■ Power Supply 2.5V ± 0.2V ■ Power Supply 2.6V ± 0.1V for DDR400 ■ tRAS lockout supported ■ Concurrent auto precharge option is supported ■ Industrial Temperature (TA): -40C to +85C Note: (-5B) Supports PC3200 module with 2.5-3-3 timing (-5) Supports PC3200 module with 3-3-3 timing (-6) Supports PC2700 module with 2.5-3-3 timing (-7) Supports PC2100 module with 2-2-2 timing Description The V58C2256(804/404/164)SCI is a four bank DDR DRAM organized as 4 banks x 8Mbit x 8 (804), 4 banks x 4Mbit x 16 (164), or 4 banks x 16Mbit x 4 (404). The V58C2256(804/404/164)SCI achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. All of the control, address, circuits are synchronized with the positive edge of an externally supplied clock. I/O transactions are occurring on both edges of DQS. Operating the four memory banks in an interleaved fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A se- quential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device. Device Usage Chart Operating Temperature Range Package Outline JEDEC 66 TSOP II 60 FBGA -40°C to +85°C • V58C2256(804/404/164)SCI Rev.1.4 March 2007 CK Cycle Time (ns) -5B -5 -6 ••• 1 -7 • Power Std. • L • Temperature Mark I Datasheet pdf - http://www.DataSheet4U.net/ 1 page www.DataSheet.co.kr ProMOS TECHNOLOGIES V58C2256(804/404/164)SCI Block Diagram 64M x 4 Column Addresses A0 - A9, A11, AP, BA0, BA1 Row Addresses A0 - A12, BA0, BA1 Column address counter Column address buffer Row address buffer Refresh Counter Row decoder Memory array Bank 0 8192 x 1024 x8 Row decoder Memory array Bank 1 8192 x 1024 x8 Row decoder Memory array Bank 2 8192 x 1024 x8 Row decoder Memory array Bank 3 8192 x 1024 x8 CK, CK DQS Input buffer Output buffer DLL Strobe Gen. DQ0-DQ3 Data Strobe Control logic & timing generator V58C2256(804/404/164)SCI Rev. 1.4 March 2007 5 Datasheet pdf - http://www.DataSheet4U.net/ 5 Page www.DataSheet.co.kr ProMOS TECHNOLOGIES V58C2256(804/404/164)SCI Mode Register Set Timing T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 tCK tRP tMRD CK, CK Command Pre- All MRS/EMRS ANY Mode Register set (MRS) or Extended Mode Register Set (EMRS) can be issued only when all banks are in the idle state. If a MRS command is issued to reset the DLL, then an additional 200 clocks must occur prior to issuing any new command to allow time for the DLL to lock onto the clock. Burst Mode Operation Burst Mode Operation is used to provide a constant flow of data to memory locations (Write cycle), or from memory locations (Read cycle). Two parameters define how the burst mode will operate: burst sequence and burst length. These parameters are programmable and are determined by address bits A0—A3 during the Mode Register Set command. Burst type defines the sequence in which the burst data will be delivered or stored to the SDRAM. Two types of burst sequence are supported: sequential and interleave. The burst length controls the number of bits that will be output after a Read command, or the number of bits to be input after a Write command. The burst length can be programmed to values of 2, 4, or 8. See the Burst Length and Sequence table below for programming information. Burst Length and Sequence Burst Length 2 4 8 Starting Length (A2, A1, A0) xx0 xx1 x00 x01 x10 x11 000 001 010 011 100 101 110 111 Sequential Mode 0, 1 1, 0 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0,1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7, 0 2, 3, 4, 5, 6, 7, 0, 1 3, 4, 5, 6, 7, 0, 1, 2 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 0, 1, 2, 3, 4 6, 7, 0, 1, 2, 3, 4, 5 7, 0, 1, 2, 3, 4, 5, 6 Interleave Mode 0, 1 1, 0 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 0,1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0 V58C2256(804/404/164)SC*I Rev. 1.4 March 2007 11 Datasheet pdf - http://www.DataSheet4U.net/ 11 Page

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