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PDF CY8CLED16P01 Data sheet ( Hoja de datos )
| Número de pieza | CY8CLED16P01 | |
| Descripción | Powerline Communication Solution Integrated Powerline Modem PHY | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY8CLED16P01
Powerline Communication Solution
Features
■ Powerline Communication Solution
❐ Integrated Powerline Modem PHY
❐ Frequency Shift Keying Modulation
❐ Configurable baud rates up to 2400 bps
❐ Powerline Optimized Network Protocol
❐ Integrates Data Link, Transport, and Network Layers
❐ Supports Bidirectional Half Duplex Communication
❐ 8-bit CRC Error Detection to Minimize Data Loss
❐ I2C enabled Powerline Application Layer
❐ Supports I2C Frequencies of 50, 100, and 400 kHz
❐ Reference Designs for 110V/240V AC and 12V/24V AC/DC
Powerlines
❐ Reference Designs comply with CENELEC EN
50065-1:2001 and FCC Part 15
■ HB LED Controller
❐ Configurable Dimmers Support up to 16 Independent LED
Channels
❐ 8 to 32 Bits of Resolution per Channel
❐ PrISM™ Modulation technology to reduce radiated EMI and
Low Frequency Blinking
❐ Additional communication interfaces for lighting control such
as DALI, DMX512 etc.
■ Powerful Harvard Architecture Processor
❐ M8C Processor Speeds to 24 MHz
❐ Two 8x8 Multiply, 32-Bit Accumulate
■ Programmable System Resources (PSoC® Blocks)
❐ 12 Rail-to-Rail Analog PSoC Blocks provide:
• Up to 14-Bit ADCs
• Up to 9-Bit DACs
• Programmable Gain Amplifiers
• Programmable Filters and Comparators
❐ 16 Digital PSoC Blocks provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• CRC and PRS Modules
• Up to Four Full Duplex UARTs
• Multiple SPITM Masters or Slaves
• Connectable to all GPIO Pins
❐ Complex Peripherals by Combining Blocks
■ Flexible On-Chip Memory
❐ 32 KB Flash Program Storage 50,000 Erase or Write Cycles
❐ 2 KB SRAM Data Storage
❐ EEPROM Emulation in Flash
■ Programmable Pin Configurations
❐ 25 mA Sink, 10 mA Source on all GPIOs
❐ Pull Up, Pull Down, High Z, Strong, or Open-drain Drive
Modes on all GPIOs
❐ Up to 12 Analog Inputs on GPIO
❐ Configurable Interrupt on all GPIO
■ Additional System Resources
❐ I2C Slave, Master, and Multi-Master to 400 kHz
❐ Watchdog and Sleep Timers
❐ User-Configurable Low Voltage Detection
❐ Integrated Supervisory Circuit
❐ On-Chip Precision Voltage Reference
■ Complete Development Tools
❐ Free Development Software (PSoC Designer™)
❐ Full Featured In-Circuit Emulator (ICE) and Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128 KB Trace Memory
❐ Complex Events
❐ C Compilers, Assembler, and Link
Logic Block Diagram
Powerline Communication Solution
Powerline
Network Protocol
Physical Layer
FSK Modem
PLC Core
Embedded Application
Programmable
System Resources
Digital and Analog
Peripherals
Additional System
Resources
MAC, Decimator, I2C,
SPI, UART etc.
PSoC Core
Modulation
Technology
PrISM, PWM etc.
Additional
Communication
Interface
DALI, DMX512
HB LED
Controller
Powerline Transceiver Packet
AC/DC Powerline Coupling Circuit
(110V/240V AC, 12V/24V AC/DC etc.)
Powerline
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-49263 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 17, 2011
Datasheet pdf - http://www.DataSheet4U.net/
1 page  
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CY8CLED16P01
2.3.3 Packet Header
The packet header contains the first 6 bytes of the packet when
1-byte logical addressing is used. When 8-byte physical
addressing is used, the source and destination addresses each
contain 8 bytes. In this case, the header can consist of a
maximum of 20 bytes. Unused fields marked RSVD are for future
expansion and are transmitted as bit 0. Table 2-2 describes the
PLT packet header fields in detail.
Table 2-2. Powerline Transceiver (PLT) Packet Header
Field No. of
Name Bits
SA Type 1
DA Type 2
Service
Type
Response
1
1
Seq Num 4
Header
CRC
4
Tag Description
Source
Address
Type
Destination
Address
Type
Response
Sequence
Number
0 – Logical Addressing
1 – Physical Addressing
00 – Logical Addressing
01 – Group Addressing
10 – Physical Addressing
11 – Invalid
0 – Unacknowledged Messaging
1 – Acknowledged Messaging
0 - Not an acknowledgement or
response packet
1 - Acknowledgement or response
packet
4-bit unique identifier for each
packet between source and desti-
nation.
4-bit CRC value. This enables the
receiver to suspend receiving the
rest of the packet if its header is
corrupted
2.3.4 Payload
The packet payload has a length of 0 to 31 bytes. Payload
content is user defined and can be read or written through I2C.
2.3.5 Packet CRC
The last byte of the packet is an 8-bit CRC value used to check
packet data integrity. This CRC calculation includes the header
and payload portions of the packet and is in addition to the
powerline packet header CRC.
2.3.6 Sequence Numbering
The sequence number is increased for every new unique packet
transmitted. If in acknowledged mode and an acknowledgment
is not received for a given packet, that packet will be re-trans-
mitted (if TX_Retry > 0) with the same sequence number. If in
unacknowledged mode, the packet will be transmitted (TX_Retry
+ 1) times with the same sequence number.
If the receiver receives consecutive packets from the same
source address with the same sequence number and packet
CRC, it does not notify the host of the reception of the duplicate
packet. If in acknowledged mode, it still sends an acknowl-
edgment so that the transmitter knows that the packet was
received.
2.3.7 Addressing
The CY8CLED16P01 has three modes of addressing:
■ Logical addressing: Every CY8CLED16P01 node can have
either a 8-bit logical address or a 16-bit logical address. The
logical address of the PLC Node is set by the local application
or by a remote node on the Powerline.
■ Physical addressing: Every CY8CLED16P01 has a unique
64-bit physical address.
■ Group addressing: This is explained in the next section.
2.3.8 Group Membership
Group membership enables the user to multicast messages to
select groups. The CY8CLED16P01 supports two types of group
addressing:
■ Single Group Membership – The network protocol supports up
to 256 different groups on the network in this mode. In this
mode, each PLC node can only be part of a single group. For
example, multiple PLC nodes can be part of Group 131.
■ Multiple Group Membership – The network protocol supports
eight different groups in this mode and each PLC node can be
a part of multiple groups. For example, a single PLC node can
be a part of Group 3, Group 4, and Group 7 at the same time.
Both of these membership modes can also be used together for
group membership. For example, a single PLC node can be a
part of Group 131 and also multiple groups such as Group 3,
Group 4, and Group 7.
The group membership ID for broadcasting messages to all
nodes in the network is 0x00.
The service type is always set to Unacknowledgment Mode in
Group Addressing Mode. This is to avoid acknowledgment
flooding on the powerline during multicast.
2.3.9 Remote Commands
In addition to sending normal data over the Powerline, the
CY8CPLC10 can also send (and request) control information to
(and from) another node on the network. The type of remote
command to transmit is set by the TX_CommandID register and
when received, is stored in the RX_CommandID register.
When a control command (Command ID = 0x01 - 0x08 and 0x0C
- 0x0F) is received, the protocol will automatically process the
packet (if Lock_Configuration is '0'), respond to the initiator, and
notify the host of the successful transmission and reception.
When the send data command (ID 0x09) or request for data
command (ID 0x0A) is received, the protocol will reply with an
acknowledgment packet (if TX_Service_Type = '1'), and notify
the host of the new received data. If the initiator doesn't receive
the acknowledgment packet within 500ms, it will notify the host
of the no acknowledgment received condition.
When a response command (ID 0x0B) is received by the initiator
within 1.5s of sending the request for data command, the
protocol will notify the host of the successful transmission and
reception. If the response command is not received by the
initiator within 1.5s, it will notify the host of the no response
received condition.
The host is notified by updating the appropriate values in the
INT_Status register (including Status_Value_Change).
The command IDs 0x30-0xff can be used for custom commands
that would be processed by the external host (e.g. set an LED
color, get a temperature/voltage reading). The available remote
commands are described in Table 2-3 on page 6 with the
respective Command IDs.
Document Number: 001-49263 Rev. *J
Page 5 of 58
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CY8CLED16P01
4. PSoC Core
The CY8CLED16P01 is based on the Cypress PSoC® 1 archi-
tecture. The PSoC platform consists of many Programmable
System-on-chip Controller devices. These devices are designed
to replace multiple traditional MCU-based system components
with one, low cost single-chip programmable device. PSoC
devices include configurable blocks of analog and digital logic,
and programmable interconnects. This architecture enables the
user to create customized peripheral configurations that match
the requirements of each individual application. Additionally, a
fast CPU, Flash program memory, SRAM data memory, and
configurable I/Os are included in a range of convenient pinouts
and packages.
The PSoC architecture, as shown in Figure 4-1., consists of four
main areas: PSoC Core, Digital System, Analog System, and
System Resources. Configurable global busing enables all the
device resources to be combined into a complete custom
system. The CY8CLED16P01 family can have up to five I/O ports
that connect to the global digital and analog interconnects,
providing access to 16 digital blocks and 12 analog blocks.
The PSoC Core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
GPIO (General Purpose I/O).
Figure 4-1. PSoC Architecture
Port 7 Port 6
Port 5
Port 4
Port 3
Port 2
Port 1
Port 0
Analog
Drivers
SYSTEM BUS
The M8C CPU core is a powerful processor with speeds up to
24 MHz, providing a 4 MIPS 8-bit Harvard architecture micropro-
cessor. The CPU uses an interrupt controller with 25 vectors, to
simplify programming of realtime embedded events. Program
execution is timed and protected using the included Sleep and
Watchdog timers (WDT).
Memory encompasses 32 KB of Flash for program storage, 2 KB
of SRAM for data storage, and up to 2 KB of EEPROM emulated
using Flash. Program Flash uses four protection levels on blocks
of 64 bytes, enabling customized software IP protection.
The PSoC device incorporates flexible internal clock generators,
including a 24 MHz IMO (internal main oscillator) accurate to 2.5
percent over temperature and voltage. The 24 MHz IMO can also
be doubled to 48 MHz for the digital system use. A low power
32 kHz ILO (internal low speed oscillator) is provided for the
sleep timer and WDT. If crystal accuracy is desired, the ECO
(32.768 kHz external crystal oscillator) is available for use as a
Real Time Clock (RTC) and can optionally generate a
crystal-accurate 24 MHz system clock using a PLL. When
operating the Powerline Transceiver (PLT) user module, the
ECO must be selected to ensure accurate protocol timing. The
clocks, together with programmable clock dividers (as a System
Resource), provide the flexibility to integrate almost any timing
requirement into the PSoC device.
PSoC GPIOs provide connection to the CPU, digital, and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, enabling great flexibility in external inter-
facing. Every pin also has the capability to generate a system
interrupt on high level, low level, and change from last read.
Global Digital Interconnect
Global Analog Interconnect
SRAM
2K
Interrupt
Controller
SROM Flash 32K PSoC CORE
CPU Core (M8C)
Sleep and
Watchdog
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
Digital
Block
Array
ANALOG SYSTEM
Analog
Block
Array
Analog
Ref.
Analog
Input
Muxing
Digital
Clocks
Two
Multiply
Accums.
Decimator I2C
POR and LVD
System Resets
SYSTEM RESOURCES
Internal
Voltage
Ref.
Document Number: 001-49263 Rev. *J
Page 11 of 58
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