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Número de pieza IT8512F
Descripción Embedded Controller
Fabricantes ITE　
Logotipo ITE Logotipo



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IT8512E/F
Embedded Controller
Preliminary Specification 0.4.1
ITE TECH. INC.
Specification subject to Change without notice, AS IS and for reference only. For purchasing, please contact sales
representatives.
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IT8512F pdf
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IT8512E/F
6.2.4.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 46
6.2.4.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 46
6.2.4.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 46
6.2.4.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) ............................ 47
6.2.4.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 47
6.2.4.7 Interrupt Request Type Select (IRQTP) .................................................................. 47
6.2.5 KBC / Mouse Interface Configuration Registers .................................................................. 47
6.2.5.1 Logical Device Activate Register (LDA)................................................................... 47
6.2.5.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 47
6.2.5.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 48
6.2.5.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 48
6.2.5.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) ............................ 48
6.2.5.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 48
6.2.5.7 Interrupt Request Type Select (IRQTP) .................................................................. 48
6.2.6 KBC / Keyboard Interface Configuration Registers.............................................................. 48
6.2.6.1 Logical Device Activate Register (LDA)................................................................... 49
6.2.6.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 49
6.2.6.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 49
6.2.6.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 49
6.2.6.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) ............................ 49
6.2.6.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 49
6.2.6.7 Interrupt Request Type Select (IRQTP) .................................................................. 49
6.2.7 Shared Memory/Flash Interface (SMFI) Configuration Registers ........................................ 50
6.2.7.1 Logical Device Activate Register (LDA)................................................................... 50
6.2.7.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 50
6.2.7.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 50
6.2.7.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 50
6.2.7.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) ............................ 51
6.2.7.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 51
6.2.7.7 Interrupt Request Type Select (IRQTP) .................................................................. 51
6.2.7.8 Shared Memory Configuration Register (SHMC) .................................................... 51
6.2.8 BRAMLD Configuration Registers........................................................................................ 52
6.2.8.1 Logical Device Activate Register (LDA)................................................................... 52
6.2.8.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 52
6.2.8.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 52
6.2.8.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 52
6.2.8.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) ............................ 53
6.2.8.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 53
6.2.8.7 Interrupt Request Type Select (IRQTP) .................................................................. 53
6.2.8.8 P80L Begin Index (P80LB) ...................................................................................... 53
6.2.8.9 P80L End Index (P80LE)......................................................................................... 53
6.2.8.10 P80L Current Index (P80LC) ................................................................................... 53
6.2.9 Power Management I/F Channel 1 Configuration Registers................................................ 54
6.2.9.1 Logical Device Activate Register (LDA)................................................................... 54
6.2.9.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 54
6.2.9.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 54
6.2.9.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 54
6.2.9.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) ............................ 55
6.2.9.6 Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)................... 55
6.2.9.7 Interrupt Request Type Select (IRQTP) .................................................................. 55
6.2.10 Power Management I/F Channel 2 Configuration Registers................................................ 55
6.2.10.1 Logical Device Activate Register (LDA)................................................................... 55
6.2.10.2 I/O Port Base Address Bits [15:8] for Descriptor 0 (IOBAD0[15:8]) ........................ 56
6.2.10.3 I/O Port Base Address Bits [7:0] for Descriptor 0 (IOBAD0[7:0]) ............................ 56
6.2.10.4 I/O Port Base Address Bits [15:8] for Descriptor 1 (IOBAD1[15:8]) ........................ 56
6.2.10.5 I/O Port Base Address Bits [7:0] for Descriptor 1 (IOBAD1[7:0]) ............................ 56
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ii IT8512E/F V0.4.1
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IT8512F arduino
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IT8512E/F
7.5.2 Features ............................................................................................................................. 173
7.5.3 EC Interface Registers ....................................................................................................... 173
7.5.3.1 General Control Register (GCR) ........................................................................... 174
7.5.3.2 Port Data Registers A-J (GPDRA-GPDRJ) ........................................................... 174
7.5.3.3 Port Data Mirror Registers A-J (GPDMRA-GPDMRJ)........................................... 174
7.5.3.4 Port Control n Registers (GPCRn, n = A0-I7)........................................................ 175
7.5.3.5 Output Type Registers H (GPOTH)....................................................................... 176
7.5.4 Alternate Function Selection .............................................................................................. 177
7.5.5 Programming Guide ........................................................................................................... 181
7.6 EC Clock and Power Management Controller (ECPM) .................................................................. 182
7.6.1 Overview............................................................................................................................. 182
7.6.2 Features ............................................................................................................................. 182
7.6.3 EC Interface Registers ....................................................................................................... 182
7.6.3.1 Clock Gating Control 1 Register (CGCTRL1R) ..................................................... 183
7.6.3.2 Clock Gating Control 2 Register (CGCTRL2R) ..................................................... 184
7.6.3.3 Clock Gating Control 3 Register (CGCTRL3R) ..................................................... 184
7.6.3.4 PLL Control (PLLCTRL) ........................................................................................ 185
7.6.3.5 Auto Clock Gating (AUTOCG)............................................................................... 185
7.6.3.6 PLL Frequency (PLLFREQR)................................................................................ 186
7.7 SM Bus Interface (SMB) ................................................................................................................. 187
7.7.1 Overview............................................................................................................................. 187
7.7.2 Features ............................................................................................................................. 187
7.7.3 Functional Description........................................................................................................ 187
7.7.3.1 SMBUS Master Interface....................................................................................... 187
7.7.3.2 SMBUS Porting Guide ........................................................................................... 188
7.7.4 EC Interface Registers ....................................................................................................... 192
7.7.4.1 Host Status Register (HOSTA).............................................................................. 193
7.7.4.2 Host Control Register (HOCTL)............................................................................. 194
7.7.4.3 Host Command Register (HOCMD) ...................................................................... 194
7.7.4.4 Transmit Slave Address Register (TRASLA) ........................................................ 195
7.7.4.5 Data 0 Register (D0REG)...................................................................................... 195
7.7.4.6 Data 1 Register (D1REG)...................................................................................... 195
7.7.4.7 Host Block Data Byte Register (HOBDB) .............................................................. 195
7.7.4.8 Packet Error Check Register (PECERC)............................................................... 196
7.7.4.9 SMBUS Pin Control Register (SMBPCTL) ............................................................ 196
7.7.4.10 Host Control Register 2 (HOCTL2)........................................................................ 196
7.7.4.11 4.7 μs Low Register (4P7USL) .............................................................................. 197
7.7.4.12 4.0 μs Low Register (4P0USL) .............................................................................. 197
7.7.4.13 300 ns Register (300NSREG) ............................................................................... 197
7.7.4.14 250 ns Register (250NSREG) ............................................................................... 197
7.7.4.15 25 ms Register (25MSREG).................................................................................. 198
7.7.4.16 45.3 μs Low Register (45P3USLREG) .................................................................. 198
7.7.4.17 45.3 μs High Register (45P3USHREG)................................................................. 198
7.7.4.18 4.7 μs And 4.0 μs High Register (4p7A4P0H) ....................................................... 198
7.8 PS/2 Interface ................................................................................................................................. 199
7.8.1 Overview............................................................................................................................. 199
7.8.2 Features ............................................................................................................................. 199
7.8.3 Functional Description........................................................................................................ 199
7.8.3.1 Hardware Mode Selected ...................................................................................... 199
7.8.3.2 Software Mode Selected ....................................................................................... 200
7.8.4 EC Interface Registers ....................................................................................................... 200
7.8.4.1 PS/2 Control Register 1-3 (PSCTL1-3) ................................................................. 201
7.8.4.2 PS/2 Interrupt Control Register 1-3 (PSINT1-3).................................................... 201
7.8.4.3 PS/2 Status Register 1-3 (PSSTS1-3)................................................................... 202
7.8.4.4 PS/2 Data Register 1-3 (PSDAT1-3) ..................................................................... 202
7.9 Digital To Analog Converter (DAC)................................................................................................. 203
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viii IT8512E/F V0.4.1
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