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PDF IT6603 Data sheet ( Hoja de datos )
| Número de pieza | IT6603 | |
| Descripción | Single-Link HDMI 1.3 Receiver | |
| Fabricantes | ITE TECH | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de IT6603 (archivo pdf) en la parte inferior de esta página. Total 35 Páginas | ||
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IT6603
Single-Link HDMI 1.3 Receiver
ITE TECH. INC.
www.ite.com.tw
Feb-2009 Rev:1.0 1/35
Datasheet pdf - http://www.DataSheet4U.net/
1 page  
www.DataSheet.co.kr
IT6603
Pin Description
Digital Video Onput Pins
Pin Name Direction Description
QE[35:26] Output Digital Video Output Pins. Channel swap and
QE[23:14]
MSB-LSB reversal are supported through register
QE[11:2]
setting.
PCLK
Output
DE
HSYNC
VSYNC
EVENODD
Output
Output
Output
Output
Output data clock. The backend controller should
use the rising edge of PCLK to strobe QE[35:2]
Data enable
Horizontal sync. signal
Vertical sync. signal
Indicates whether the current field is Even or Odd
for interlaced format
Type
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Pin No.
1-3, 7-10, 13-14,
96-99, 102-105,
108-109, 112-115,
118-121, 124-125,
128
5
17
18
19
20
Digital Audio Onput Pins
Pin Name Direction Description
XTALIN
Input
Crystal clock input (for Audio PLL)
XTALOUT Output Crystal clock output (for Audio PLL)
MCLK
Output Audio master clock
SCK_DCLK Output I2S serial clock output, doubles as DSD clock
WS_DR0
Output I2S word select output, doubles as DSD Serial Right CH0 data
output
I2S0_DL0 Output I2S serial data output, doubles as DSD Serial Left CH0 data
output
I2S1_DR1 Output I2S serial data output, doubles as DSD Serial Right CH1 data
output
I2S2_DL1 Output I2S serial data output, doubles as DSD Serial Left CH2 data
output
I2S3_DR2 Output I2S serial data output, doubles as DSD Serial Right CH2 data
output
SPDIF_DL2 Output S/PDIF audio output, doubles as DSD Serial Left CH2 data
output
MUTE_DR3 Output Mute output, doubles as DSD Serial Right CH3 data output
DSD_DL3 Output DSD Serial Left CH3 data output
Type
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Pin No.
85
84
79
76
75
LVTTL
71
LVTTL
72
LVTTL
73
LVTTL
74
LVTTL
68
LVTTL
LVTTL
66
67
www.ite.com.tw
Feb-2009 Rev:1.0 5/35
Datasheet pdf - http://www.DataSheet4U.net/
5 Page 
www.DataSheet.co.kr
IT6603
The IT6603 also provides automatic video mode detection. The system controller can elect to check
out respective status registers to get the informations.
Color Video
Space Format
RGB 4:4:4
4:4:4
YCbCr
4:2:2
Bus
Width
24
30
24
30
16/20
8/10
Hsync/
Vsync
Separate
Separate
Separate
Embedded
Separate
Embedded
480i
13.5
13.5
13.5
13.5
13.5
13.5
27
27
Output Pixel Clock Frequency (MHz)
480p
XGA
720p 1080i SXGA 1080p UXGA
27 65 74.25 74.25 108 148.5 162
27 65 74.25 74.25 108 148.5
27 65 74.25 74.25 108 148.5 162
27 65 74.25 74.25 108 148.5
27
74.25 74.25
148.5
27
74.25 74.25
148.5
54 148.5 148.5
54 148.5 148.5
Table 1. Output video formats supported by the IT6603
Notes:
1. Table cells that are left blanks are those format combinations that are not supported by the IT6603.
2. Output channel number is defined by the way the three color components (either R, G & B or Y, Cb & Cr) are
arranged. Refer to Video Data Bus Mappings for better understanding.
3. Embedded sync signals are defined by CCIR-656 standard, using SAV/EAV sequences of FF, 00, 00, XY.
4. The lowest TMDS clock frequency specified by the HDMI standard is 25MHz for 640X480@60Hz.
Audio Clock Recovery and Data Processing
The audio processing block in the HDMI Sink is crucial to the system performance since human
hearing is susceptive to audio imperfection. The IT6603 prides itself in outstanding audio recovery
performances. In addition, the audio clock recovery PLL uses an external crystal reference so as to
provide stable and reliable audio clocks for all audio output formats.
The IT6603 supports all audio formats and interfaces specified by the HDMI Specification v1.3 through
I2S, S/PDIF and optional one-bit audio outputs. The one-bit audio outputs take on the pins used by I2S
outputs, so only one between the two could be activated at a time.
I2S
Four I2S outputs are provided to support 8-channel uncompressed audio data at up to 192kHz sample
rate. A coherent multiple (master) clock MCLK is generated at pin 79 to facilitate proper functions of
mainstream backend audio DAC ICs. The supported multiplied factor and sample frequency as well as
the resultant MCLK frequencies are summarized in Table 2.
www.ite.com.tw
Feb-2009 Rev:1.0 11/35
Datasheet pdf - http://www.DataSheet4U.net/
11 Page | ||
| Páginas | Total 35 Páginas | |
| PDF Descargar | [ Datasheet IT6603.PDF ] | |
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