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25T80 데이터시트, 핀배열, 회로
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EN25T80
EN25T80
8 Mbit Uniform Sector, Serial Flash Memory with Dual Data Mode
FEATURES
Single power supply operation
- Full voltage range: 2.7-3.6 volt
8 Mbit Serial Flash
- 8 M-bit/1024 K-byte/4096 pages
- 256 bytes per programmable page
High performance
- 100MHz clock rate
- dual data mode
Low power consumption
- 5 mA typical active current
- 1 μA typical power down current
Uniform Sector Architecture:
- 256 sectors of 4-Kbyte
- 16 blocks of 64-Kbyte
- Any sector or block can be
erased individually
Software and Hardware Write Protection:
- Write Protect all or portion of memory via
software
- Enable/Disable protection with WP# pin
High performance program/erase speed
- Page program time: 1.5ms typical
- Sector erase time: 150ms typical
- Block erase time 800ms typical
- Chip erase time: 10 Seconds typical
Lockable 256 byte OTP security sector
Minimum 100K endurance cycle
Package Options
- 8 pins SOP 200mil body width
- 8 pins PDIP
- 8 contact VDFN
- All Pb-free packages are RoHS compliant
Commercial and industrial temperature
Range
GENERAL DESCRIPTION
The EN25T80 is a 8M-bit (1024K-byte) Serial Flash memory, with advanced write protection
mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to
256 bytes at a time, using the Page Program instruction.
The EN25T80 is designed to allow either single Sector at a time or full chip erase operation. The
EN25T80 can be configured to protect part of the memory as the software protected mode. The device
can sustain a minimum of 100K program/erase cycles on each sector.
This Data Sheet may be revised by subsequent versions 1
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. A, Issue Date: 2006/11/6
Datasheet pdf - http://www.DataSheet4U.net/




25T80 pdf, 반도체, 판매, 대치품
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EN25T80
MEMORY ORGANIZATION
The memory is organized as:
z 1,048,576 bytes
z Uniform Sector Architecture
16 blocks of 64-Kbyte
256 sectors of 4-Kbyte
z 4096 pages (256 bytes each)
Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector,
Block or Chip Erasable but not Page Erasable.
This Data Sheet may be revised by subsequent versions
4
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. A, Issue Date: 2006/11/6
Datasheet pdf - http://www.DataSheet4U.net/

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25T80 전자부품, 판매, 대치품
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EN25T80
Status Register. The Status Register contains a number of status and control bits that can be read or set
(as appropriate) by specific instructions.
WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status
Register, Program or Erase cycle.
WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the
area to be software protected against Program and Erase instructions.
Mode1, Mode0 bits. Default value is SPI mode (00), user can change this value by change mode
commands to change the interface mode. This device also support SP2 mode (01).
SP2 mode : command/address/data all transmitting with 2 bits
SRP bit / OTP_LOCK bit The Status Register Protect (SRP) bit is operated in conjunction with the Write
Protect (WP#) signal. The Status Register Protect (SRP) bit and Write Protect (WP#) signal allow the
device to be put in the Hardware Protected mode. In this mode, the non-volatile bits of the Status Register
(SRP, BP2, BP1, BP0) become read-only bits.
In OTP mode, this bit is served as OTP_LOCK bit, user can read/program/erase OTP sector as normal
sector while OTP_LOCK value is equal 0, after OTP_LOCK is programmed with 1 by WRSR command,
the OTP sector is protected from program and erase operation. The OTP_LOCK bit can only be
programmed once.
Note : In OTP mode, the WRSR command will ignore any input data and program OTP_LOCK bit to 1, user
must clear the protect bits before enter OTP mode and program the OTP code, then execute WRSR command
to lock the OTP sector before leaving OTP mode.
Write Protection
Applications that use non-volatile memory must take into consideration the possibility of noise and other
adverse system conditions that may compromise data integrity. To address this concern the EN25T80
provides the following data protection mechanisms:
z Power-On Reset and an internal timer (tPUW) can provide protection against inadvertent changes
while the power supply is outside the operating specification.
z Program, Erase and Write Status Register instructions are checked that they consist of a number of
clock pulses that is a multiple of eight, before they are accepted for execution.
z All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the
Write Enable Latch (WEL) bit . This bit is returned to its reset state by the following events:
– Power-up
– Write Disable (WRDI) instruction completion or Write Status Register (WRSR) instruction
completion or Page Program (PP) instruction completion or Sector Erase (SE)instruction
completion or Block Erase (BE) instruction completion or Chip Erase (CE) instruction completion
z The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be configured as read-only. This
is the Software Protected Mode (SPM).
z The Write Protect (WP#) signal allows the Block Protect (BP2, BP1, BP0) bits and Status Register
Protect (SRP) bit to be protected. This is the Hardware Protected Mode (HPM).
z In addition to the low power consumption feature, the Deep Power-down mode offers extra software
protection from inadvertent Write, Program and Erase instructions, as all instructions are ignored
except one particular instruction (the Release from Deep Power-down instruction).
This Data Sheet may be revised by subsequent versions
7
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. A, Issue Date: 2006/11/6
Datasheet pdf - http://www.DataSheet4U.net/

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