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PDF 68HC11A1FN Data sheet ( Hoja de datos )
| Número de pieza | 68HC11A1FN | |
| Descripción | MC68HC11A1 | |
| Fabricantes | Freescale Semiconductor | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR
TECHNICAL DATA
Technical Summary
8-Bit Microcontrollers
Order this document
by MC68HC11A8TS/D
MC68HC11A8
MC68HC11A1
MC68HC11A0
1 Introduction
The MC68HC11A8, MC68HC11A1, and MC68HC11A0 high-performance microcontroller units (MCUs)
are based on the M68HC11 Family. These high speed, low power consumption chips have multiplexed
buses and a fully static design. The chips can operate at frequencies from 3 MHz to dc. The three MCUs
are created from the same masks; the only differences are the value stored in the CONFIG register, and
whether or not the ROM or EEPROM is tested and guaranteed.
For detailed information about specific characteristics of these MCUs, refer to the M68HC11 Reference
Manual (M68HC11RM/AD).
1.1 Features
• M68HC11 CPU
• Power Saving STOP and WAIT Modes
• 8 Kbytes ROM
• 512 Bytes of On-Chip EEPROM
• 256 Bytes of On-Chip RAM (All Saved During Standby)
• 16-Bit Timer System
— 3 Input Capture Channels
— 5 Output Compare Channels
• 8-Bit Pulse Accumulator
• Real-Time Interrupt Circuit
• Computer Operating Properly (COP) Watchdog System
• Synchronous Serial Peripheral Interface (SPI)
• Asynchronous Nonreturn to Zero (NRZ) Serial Communications Interface (SCI)
• 8-Channel, 8-Bit Analog-to-Digital (A/D) Converter
• 38 General-Purpose Input/Output (I/O) Pins
— 15 Bidirectional I/O Pins
— 11 Input-Only Pins and 12 Output-Only Pins (Eight Output-Only Pins in 48-Pin Package)
• Available in 48-Pin Dual In-Line Package (DIP) or 52-Pin Plastic Leaded Chip Carrier (PLCC)
This document contains information on a new product. Specifications and information herein are subject to change without notice.
© MOTOROLA INC., 1991, 1996
1 page  
XTAL 8
1 46 PE5/AN5
PC0/A0/D0 9
45 PE1/AN1
PC1/A1/D1 10
44 PE4/AN4
PC2/A2/D2 11
43 PE0/AN0
PC3/A3/D3 12
42 PB0/A8
PC4/A4/D4 13
41 PB1/A9
PC5/A5/D5 14
40 PB2/A10
PC6/A6/D6 15
39 PB3/A11
PC7/A7/D7 16
38 PB4/A12
RESET 17
37 PB5/A13
XIRQ 18
36 PB6/A14
IRQ 19
35 PB7/A15
PD0/RxD 20
34 PA0/IC3
Figure 2 52-Pin PLCC Pin Assignments
MC68HC11A8
MC68HC11A8TS/D
MOTOROLA
5
5 Page 
HPRIO — Highest Priority I-Bit Interrupt and Miscellaneous
$103C
RESET:
Bit 7
RBOOT
—
6
SMOD
—
5
MDA
—
4 3 2 1 Bit 0
IRV PSEL3 PSEL2 PSEL1 PSEL0
—0 1 0 1
RBOOT, SMOD, and MDA reset depend on conditions at reset and can only be written in special modes
(SMOD = 1).
RBOOT — Read Bootstrap ROM
0 = Bootloader ROM disabled and not in map
1 = Bootloader ROM enabled and in map at $BF40–$BFFF
SMOD —Special Mode Select
MDA — Mode Select A
Inputs
MODB
1
1
0
0
MODA
0
1
0
1
Mode
Single Chip
Expanded Multiplexed
Special Bootstrap
Special Test
Latched at Reset
RBOOT
SMOD
MDA
000
001
110
011
IRV — Internal Read Visibility
0 = No internal read visibility on external bus
1 = Data from internal reads is driven out through the external data bus
PSEL3–PSEL0 — Priority Select Bits 3 through 0
Refer to 3 Resets and Interrupts.
INIT — RAM and I/O Mapping
RESET:
Bit 7
RAM3
0
6
RAM2
0
5
RAM1
0
4
RAM0
0
3
REG3
0
2
REG2
0
$103D
1
REG1
0
Bit 0
REG0
1
RAM[3:0] —256-Byte Internal RAM Map Position
RAM[3:0] determine the upper four bits of the RAM address, positioning RAM at the selected 4K bound-
ary.
REG[3:0] —64-Byte Register Block Map Position
REG[3:0] determine the upper four bits of the register address, positioning registers at the selected 4K
boundary. Register can be written only once in the first 64 cycles out of reset in normal modes, or any
time in special modes.
MC68HC11A8
MC68HC11A8TS/D
MOTOROLA
11
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