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PDF F6P02T3 Data sheet ( Hoja de datos )
| Número de pieza | F6P02T3 | |
| Descripción | NTF6P02T3 | |
| Fabricantes | ON Semiconductor | |
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NTF6P02T3
Power MOSFET
-6.0 Amps, -20 Volts
P–Channel SOT–223
Features
• Low RDS(on)
• Logic Level Gate Drive
• Diode Exhibits High Speed, Soft Recovery
• Avalanche Energy Specified
Typical Applications
• Power Management in Portables and Battery–Powered Products, i.e.:
Cellular and Cordless Telephones and PCMCIA Cards
http://onsemi.com
–6.0 AMPERES
–20 VOLTS
RDS(on) = 44 mW (Typ.)
P–Channel
D
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol Value
Drain–to–Source Voltage
VDSS
–20
Gate–to–Source Voltage
VGS ±8.0
Drain Current (Note 1)
– Continuous @ TA = 25°C
– Continuous @ TA = 70°C
– Single Pulse (tp = 10 µs)
ID –10
ID –8.4
IDM –35
Total Power Dissipation @ TA = 25°C
PD 8.3
Operating and Storage Temperature Range
TJ, Tstg –55 to
+150
Unit
Vdc
Vdc
Adc
Apk
W
°C
Single Pulse Drain–to–Source Avalanche
Energy – Starting TJ = 25°C
(VDD = –20 Vdc, VGS = –5.0 Vdc,
IL(pk) = –10 A, L = 3.0 mH, RG = 25W)
EAS 150 mJ
Thermal Resistance
– Junction to Lead (Note 1)
– Junction to Ambient (Note 2)
– Junction to Ambient (Note 3)
RθJL
RθJA
RθJA
°C/W
15
71.4
160
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
TL 260 °C
1. Steady State.
2. When surface mounted to an FR4 board using 1″ pad size,
(Cu. Area 1.127 in2), Steady State.
3. When surface mounted to an FR4 board using minimum recommended pad
size, (Cu. Area 0.412 in2), Steady State.
G
S
MARKING
DIAGRAM
1
2
3
4 SOT–223
CASE 318E
STYLE 3
AWW
6P02
A
WW
6P02
= Assembly Location
= Work Week
= Device Code
PIN ASSIGNMENT
4 Drain
123
Gate Drain Source
ORDERING INFORMATION
Device
Package Shipping
NTF6P02T3
SOT–223 4000/Tape & Reel
© Semiconductor Components Industries, LLC, 2002
September, 2002 – Rev. 0
1
Publication Order Number:
NTF6P02T3/D
Datasheet pdf - http://www.DataSheet4U.net/
1 page  
www.DataSheet.co.kr
NTF6P02T3
TYPICAL ELECTRICAL CHARACTERISTICS
1
D = 0.5
0.2
0.1
0.1 0.05
0.02
0.01
SINGLE PULSE
0.01
1.0E-03
1.0E-02
NORMALIZED TO RqJA AT STEADY STATE (1″ PAD)
0.0175 W 0.0710 W 0.2706 W 0.5779 W 0.7086 W
CHIP
JUNCTION 0.0154 F 0.0854 F 0.3074 F 1.7891 F 107.55 F
AMBIENT
1.0E-01
1.0E+00
t, TIME (s)
1.0E+01
Figure 11. FET Thermal Response
1.0E+02
1.0E+03
INFORMATION FOR USING THE SOT–223 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the
total design. The footprint for the semiconductor packages
must be the correct size to insure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
0.079
2.0
0.15
3.8
0.091
2.3
0.091
2.3
0.079
2.0
0.059
1.5
0.059
1.5
0.059
1.5
0.248
6.3
inches
mm
http://onsemi.com
5
Datasheet pdf - http://www.DataSheet4U.net/
5 Page | ||
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| PDF Descargar | [ Datasheet F6P02T3.PDF ] | |
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