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PDF L3GD20 Data sheet ( Hoja de datos )
| Número de pieza | L3GD20 | |
| Descripción | MEMS motion sensor | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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L3GD20
MEMS motion sensor:
three-axis digital output gyroscope
Features
■ Three selectable full scales (250/500/2000
dps)
■ I2C/SPI digital output interface
■ 16 bit-rate value data output
■ 8-bit temperature data output
■ Two digital output lines (interrupt and data
ready)
■ Integrated low- and high-pass filters with user-
selectable bandwidth
■ Wide supply voltage: 2.4 V to 3.6 V
■ Low voltage-compatible IOs (1.8 V)
■ Embedded power-down and sleep mode
■ Embedded temperature sensor
■ Embedded FIFO
■ High shock survivability
■ Extended operating temperature range (-40 °C
to +85 °C)
■ ECOPACK® RoHS and “Green” compliant
Applications
■ Gaming and virtual reality input devices
■ Motion control with MMI (man-machine
interface)
■ GPS navigation systems
■ Appliances and robotics
LGA-16 (4x4x1 mm)
Description
The L3GD20 is a low-power three-axis angular
rate sensor.
It includes a sensing element and an IC interface
capable of providing the measured angular rate to
the external world through a digital interface
(I2C/SPI).
The sensing element is manufactured using a
dedicated micro-machining process developed by
STMicroelectronics to produce inertial sensors
and actuators on silicon wafers.
The IC interface is manufactured using a CMOS
process that allows a high level of integration to
design a dedicated circuit which is trimmed to
better match the sensing element characteristics.
The L3GD20 has a full scale of ±250/±500/ ±2000
dps and is capable of measuring rates with a
user-selectable bandwidth.
The L3GD20 is available in a plastic land grid
array (LGA) package and can operate within a
temperature range of -40 °C to +85 °C.
Table 1. Device summary
Order code
Temperature range (°C)
L3GD20
-40 to +85
L3GD20TR
-40 to +85
Package
LGA-16 (4x4x1 mm)
LGA-16 (4x4x1 mm)
Packing
Tray
Tape and reel
August 2011
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L3GD20
List of tables
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
INT1_THS_XL description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
INT1_THS_YH register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
INT1_THS_YH description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
INT1_THS_YL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
INT1_THS_YL description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
INT1_THS_ZH register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
INT1_THS_ZH description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
INT1_THS_ZL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
INT1_THS_ZL description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
INT1_DURATION register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
INT1_DURATION description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
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L3GD20
Mechanical and electrical specifications
2.4 Communication interface characteristics
2.4.1
SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top.
Table 6. SPI slave timing values
Symbol
Parameter
Value(1)
Min Max
Unit
tc(SPC)
fc(SPC)
tsu(CS)
th(CS)
tsu(SI)
th(SI)
tv(SO)
th(SO)
tdis(SO)
SPI clock cycle
SPI clock frequency
CS setup time
CS hold time
SDI input setup time
SDI input hold time
SDO valid output time
SDO output hold time
SDO output disable time
100 ns
10 MHz
5
8
5
15 ns
50
6
50
1. Values are guaranteed at a 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results; not
tested in production.
Figure 3. SPI slave timing diagram (a)
&6
63&
WVX &6
WVX 6,
WK 6,
WF 63&
6',
06%,1
WY 62
6'2
06%287
WK 62
WK &6
/6%,1
WGLV 62
/6%287
!-V
a. Measurement points are at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output port.
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet L3GD20.PDF ] | |
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