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PDF ISPPAC-POWR607 Data sheet ( Hoja de datos )
| Número de pieza | ISPPAC-POWR607 | |
| Descripción | In-System Programmable Power Supply | |
| Fabricantes | Lattice Semiconductor | |
| Logotipo |  |
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ispPAC-® POWR607
In-System Programmable Power Supply Supervisor,
Reset Generator and Watchdog Timer
February 2009
Data Sheet DS1011
Features
Application Block Diagram
■ Power-Down Mode ICC < 10µA
■ Programmable Threshold Monitors
• Simultaneously monitors up to six power supplies
• Programmable analog trip points (1% step size;
192 steps)
• Programmable glitch filter
• Power-off detection (75mV)
■ Embedded Programmable Timers
• Four independent timers
• 32µs to 2 second intervals for timing sequences
■ Embedded PLD for Logical Control
• Rugged 16-macrocell CPLD architecture
• 81 product terms / 28 inputs
• Implements state machines and combinatorial
functions
■ Digital I/O
• Two dedicated digital inputs
• Five programmable digital I/O pins
■ Two High-Voltage FET Drivers
• Power supply ramp up/down control
• Independently configurable for FET control or
digital output
■ Wide Supply Range (2.64V to 3.96V)
• In-system programmable through JTAG
• Industrial temperature range: -40°C to +85°C
• 32-pin QFNS (Quad Flat-pack, No lead, Saw-
singulated) package, lead-free option1
Description
Lattice’s Power Manager II ispPAC-POWR607 is a gen-
eral-purpose power-supply monitor, reset generator and
watchdog timer, incorporating both in-system program-
mable logic and analog functions implemented in non-
volatile E2CMOS® technology. The ispPAC-POWR607
device provides six independent analog input channels
to monitor power supply voltages. Two general-purpose
digital inputs are also provided for miscellaneous control
functions.
The ispPAC-POWR607 provides up to seven open-drain
digital outputs that can be used for controlling DC-DC
1. Use 32-pin QFNS package for all new designs. Refer to PCN
#13A-08 for 32-pin QFN package discontinuance.
Input Power Supply
On/Off
Manual
Reset In
DC-DC
#1
MOSFET Drivers (2)
DC-DC
#2
Power
Supply
Bus
DC-DC
#n
Voltage Supervisor
Reset Generator
Watchdog Timer
Power Down
ispPAC-POWR607
Interrupt –
Power Fail
CPU_Reset_in
WDT Trigger
Interrupt – WDT
CPU /
uProcessor
Power Up/Down Control
converters, low-drop-out regulators (LDOs) and opto-
couplers, as well as for supervisory and general-pur-
pose logic interface functions. Two of these outputs
(HVOUT1-HVOUT2) can be configured as high-voltage
MOSFET drivers. In high-voltage mode these outputs
provide 9V for driving the gates of n-channel MOSFETs
used as high-side power switches to control power sup-
ply ramp up and ramp down rate. The remaining five
digital, open drain outputs can optionally be configured
as digital inputs to sense more input signals as needed,
such as manual reset, etc.
The diagram above shows how a ispPAC-POWR607 is
used in a typical application. It controls power to the
microprocessor system, generates the CPU reset and
monitors critical power supply voltages, generating
interrupts whenever faults are detected. It also provides
a watchdog timer function to detect CPU operating and
bus timeout errors.
The ispPAC-POWR607 incorporates a 16-macrocell
CPLD. Figure 4-1 shows the analog input comparators
© 2009 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other
brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without
notice.
www.latticesemi.com
4-1
DS1011_01.6
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Lattice Semiconductor
ispPAC-POWR607 Data Sheet
Voltage Monitors
Symbol
Parameter
Conditions
RIN
CIN
VMON Range
VZ Sense
VMON Accuracy
HYST
Input resistance
Input capacitance
Programmable trip-point range
Near-ground sense threshold
Absolute accuracy of any trip-point1
Hysteresis of any trip-point (relative to
setting)
1. Guaranteed by characterization across VCC range, operating temperature, process.
Min.
55
0.075
70
High Voltage FET Drivers
Symbol
VPP
IOUTSRC
IOUTSINK
Parameter
Gate driver output voltage
Gate driver source current
(HIGH state)
Gate driver sink current
(LOW state)
Conditions
Controlled ramp setting
FET turn off mode
Min.
8.1
1.0
Power-On Reset (Internal)
Symbol
Parameter
TRST
TSTART
TBRO
Delay from VTH to start-up state
Duration of start-up state
Minimum duration brown out required to
enter reset state
TPOR
Delay from brown out to reset state
VTL Threshold below which POR is LOW1
VTH Threshold above which POR is HIGH1
VT Threshold above which POR is valid1
1. Corresponds to VCC supply voltage.
Conditions
Min.
1
2.5
0.8
Typ.
65
8
75
±0.5
1
Typ.
9
15
2.5
Typ.
Max.
75
5.811
80
1.5
Units
kΩ
pF
V
mV
%
%
Max.
9.9
Units
V
µA
mA
Max.
100
300
5
7
2.2
Units
µs
µs
µs
µs
V
V
V
4-5
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Lattice Semiconductor
ispPAC-POWR607 Data Sheet
Each comparator outputs a HIGH signal to the PLD array if the voltage at its positive terminal (VMONx pin) is
greater than its programmed trip point setting, otherwise it outputs a LOW signal.
A hysteresis of approximately 1% of the setpoint is provided by the comparators to reduce false triggering as a
result of input noise. The hysteresis provided by the voltage monitor is a function of the input divider setting.
Table 4-3 lists the typical hysteresis versus voltage monitor trip-point.
Programmable Over-Voltage and Under-Voltage Thresholds
Figure 4-9 (a) shows the power supply ramp-up and ramp-down voltage waveforms. Because of hysteresis, the
comparator outputs change state at different thresholds depending on the direction of excursion of the monitored
power supply.
Figure 4-9. (a) Power Supply Voltage Ramp-up and Ramp-down Waveform and the Resulting Comparator
Output, (b) Corresponding to Upper and Lower Trip Points
UTP
LTP
(a)
Comparator Logic Output
(b)
During power supply ramp-up the comparator output changes from logic 0 to 1 when the power supply voltage
crosses the upper trip point (UTP). During ramp down the comparator output changes from logic state 1 to 0 when
the power supply voltage crosses the lower trip point (LTP). To monitor for over voltage fault conditions, the UTP
should be used. To monitor under-voltage fault conditions, the LTP should be used.
Tables 1 and 2 show both the under-voltage and over-voltage trip points, which are automatically selected in soft-
ware depending on whether the user is monitoring for an over-voltage condition or an under-voltage condition.
4-11
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| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet ISPPAC-POWR607.PDF ] | |
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