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AD9239 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD9239은 전자 산업 및 응용 분야에서
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부품번호 AD9239 기능
기능 170 MSPS/210 MSPS/250 MSPS Serial Output 1.8 V ADC
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AD9239 데이터시트, 핀배열, 회로
Data Sheet
Quad, 12-Bit, 170 MSPS/210 MSPS/250 MSPS
Serial Output 1.8 V ADC
AD9239
FEATURES
4 ADCs in 1 package
Coded serial digital outputs with ECC per channel
On-chip temperature sensor
−95 dB channel-to-channel crosstalk
SNR = 65 dBFS with AIN = 85 MHz at 250 MSPS
SFDR = 77 dBc with AIN = 85 MHz at 250 MSPS
Excellent linearity
DNL = ±0.3 LSB (typical)
INL = ±0.7 LSB (typical)
780 MHz full power analog bandwidth
Power dissipation = 380 mW per channel at 250 MSPS
1.25 V p-p input voltage range, adjustable up to 1.5 V p-p
1.8 V supply operation
Clock duty cycle stabilizer
Serial port interface features
Power-down modes
Digital test pattern enable
Programmable header
Programmable pin functions (PGMx, PDWN)
APPLICATIONS
Communication receivers
Cable head end equipment/M-CMTS
Broadband radios
Wireless infrastructure transceivers
Radar/military-aerospace subsystems
Test equipment
GENERAL DESCRIPTION
The AD9239 is a quad, 12-bit, 250 MSPS analog-to-digital
converter (ADC) with an on-chip temperature sensor and a
high speed serial interface. It is designed to support digitizing
high frequency, wide dynamic range signals with an input
bandwidth up to 780 MHz. The output data are serialized and
presented in packet format, consisting of channel-specific
information, coded samples, and error correction code.
The ADC requires a single 1.8 V power supply and the input
clock may be driven differentially with a sine wave, LVPECL,
TTL, or LVDS. A clock duty cycle stabilizer allows high
performance at full speed with a wide range of clock duty
cycles. The on-chip reference eliminates the need for external
decoupling and can be adjusted by means of SPI control.
Various power-down and standby modes are supported. The
ADC typically consumes 145 mW per channel with the digital
link still in operation when standby operation is enabled.
FUNCTIONAL BLOCK DIAGRAM
AVDD
PDWN
DRVDD
DRGND
VIN + A
VIN – A
VCM A
VIN + B
VIN – B
VCM B
VIN + C
VIN – C
VCM C
VIN + D
VIN – D
VCM D
RBIAS
TEMPOUT
AD9239
BUF SHA
PIPELINE
ADC
12
DOUT + A
CHANNEL A
DOUT – A
BUF SHA
PIPELINE
ADC
12
DOUT + B
CHANNEL B
DOUT – B
BUF SHA
PIPELINE
ADC
12
DOUT + C
CHANNEL C
DOUT – C
BUF SHA
PIPELINE
ADC
12
DOUT + D
CHANNEL D
DOUT – D
REFERENCE
SERIAL
PORT
DATA RATE
MULTIPLIER
PGM3
PGM2
PGM1
PGM0
RESET
SCLK SDI/ SDO CSB
SDIO
CLK+ CLK–
Figure 1.
Fabricated on an advanced CMOS process, the AD9239 is avail-
able in a Pb-free/RoHS-compliant, 72-lead LFCSP package. It is
specified over the industrial temperature range of −40°C to +85°C.
PRODUCT HIGHLIGHTS
1. Four ADCs are contained in a small, space-saving package.
2. An on-chip PLL allows users to provide a single ADC
sampling clock, and the PLL distributes and multiplies up
to produce the corresponding data rate clock.
3. Coded data rate supports up to 4.0 Gbps per channel.
Coding includes scrambling to ensure proper dc common
mode, embedded clock, and error correction.
4. The AD9239 operates from a single 1.8 V power supply.
5. Flexible synchronization schemes and programmable
mode pins.
6. On-chip temperature sensor.
Rev. E
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2008–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




AD9239 pdf, 반도체, 판매, 대치품
Data Sheet
AD9239
SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, 1.25 V p-p differential input, AIN = −1.0 dBFS, DCS enabled, unless
otherwise noted.
Table 1.
Parameter1
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Offset Matching
Gain Error
Gain Matching
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
ANALOG INPUTS
Differential Input Voltage Range2
Common-Mode Voltage
Input Capacitance
Input Resistance
Analog Bandwidth, Full Power
Voltage Common Mode (VCMx)
Voltage Output
Current Drive
Temperature Sensor Output
Voltage Output
Current Drive
POWER SUPPLY
AVDD
DRVDD
IAVDD
IDRVDD
Total Power Dissipation
(Including Output Drivers)
Power-Down Dissipation
Standby Dissipation2
CROSSTALK
Overrange Condition3
Temp
AD9239BCPZ-170
Min Typ Max
12
AD9239BCPZ-210
Min Typ
Max
12
AD9239BCPZ-250
Min Typ
Max
Unit
Bits
Full Guaranteed
25°C −2 ±12
25°C 4 12
25°C −2.8 +1
+4.7
25°C 0.9 2.7
Full ±0.28 ±0.6
Full ±0.45 ±0.9
Guaranteed
−2 ±12
4 12
−2.8 +1
+4.7
0.9 2.7
±0.28
±0.6
±0.7 ±1.3
Guaranteed
−2 ±12
4 12
−2.8 +1
+4.7
0.9 2.7
±0.3 ±0.6
±0.7 ±1.3
mV
mV
% FS
% FS
LSB
LSB
Full 1.0 1.25 1.5
Full 1.4
25°C 2
Full 4.3
Full 780
1.0 1.25
1.4
2
4.3
780
1.5 1.0 1.25
1.4
2
4.3
780
1.5 V p-p
V
pF
kΩ
MHz
Full 1.4 1.44 1.5
Full 1
−1.12
Full 739
Full 50
1.4 1.44
1
−1.12
737
50
1.5 1.4 1.44
1
−1.12
734
50
1.5 V
mA
mV/°C
mV
µA
Full 1.7 1.8 1.9 1.7 1.8
Full 1.7 1.8 1.9 1.7 1.8
Full 535 570 610
Full 98 105 111
Full
1.139 1.215
1.298
Full 3
Full 152
Full −95
Full −90
3
173
−95
−90
1.9
1.9
650
120
1.386
1.7
1.7
1.8
1.8
725
123
1.526
3
195
−95
−90
1.9
1.9
775
133
1.634
V
V
mA
mA
W
mW
mW
dB
dB
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and details on how these tests were completed.
2 AVDD/DRVDD, with link established.
3 Overrange condition is specified as 6 dB above the full-scale input range.
Rev. E | Page 3 of 40

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AD9239 전자부품, 판매, 대치품
AD9239
Data Sheet
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, 1.25 V p-p differential input, AIN = –1.0 dBFS, DCS enabled, unless
otherwise noted.
Table 4.
Parameter1
CLOCK
Clock Rate
Clock Pulse Width High (tEH)
Clock Pulse Width Low (tEL)
DATA OUTPUT PARAMETERS
Data Output Period or UI
(DOUT + x, DOUT − x)
Data Output Duty Cycle
Data Valid Time
PLL Lock Time (tLOCK)
Wake-Up Time (Standby)
Wake-Up Time (Power-Down)2
Pipeline Latency
Data Rate per Channel (NRZ)
Deterministic Jitter
Random Jitter
Channel-to-Channel Bit Skew
Channel-to-Channel Packet Skew3
Output Rise/Fall Time
TERMINATION CHARACTERISTICS
Differential Termination Resistance
APERTURE
Aperture Delay (tA)
Aperture Uncertainty (Jitter)
OUT-OF-RANGE RECOVERY TIME
AD9239BCPZ-170
AD9239BCPZ-210
AD9239BCPZ-250
Temp Min Typ
Max Min Typ
Max Min Typ
Max Unit
Full 170
Full 2.65 2.9
Full 2.65 2.9
100 210
2.15 2.4
2.15 2.4
100 250
1.8 2.0
1.8 2.0
100 MSPS
ns
ns
Full 1/(16 × fCLK)
25°C 50
25°C 0.8
25°C 4
25°C 250
25°C 50
Full 40
25°C 2.72
25°C 10
25°C 6
25°C 0
25°C +1
25°C 50
1/(16 × fCLK)
50
0.8
4
250
50
40
3.36
10
6
0
+1
50
1/(16 × fCLK)
50
0.8
4
250
50
40
4.0
10
6
0
+1
50
sec
%
UI
µs
ns
μs
CLK cycles
Gbps
ps max
ps rms
sec
CLK cycles
ps
25°C 100 100 100 Ω
25°C 1.2 1.2 1.2 ns
25°C 0.2 0.2 0.2 ps rms
25°C 1 1 1 CLK cycles
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and details on how these tests were completed.
2 Receiver dependent.
3 See the Digital Start-Up Sequence section.
Rev. E | Page 6 of 40

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