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FM1608B 데이터시트 PDF




Ramtron International Corporation에서 제조한 전자 부품 FM1608B은 전자 산업 및 응용 분야에서
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부품번호 FM1608B 기능
기능 64Kb Bytewide 5V F-RAM Memory
제조업체 Ramtron International Corporation
로고 Ramtron International Corporation 로고


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FM1608B 데이터시트, 핀배열, 회로
www.DataSheet.co.kr
Preliminary
FM1608B
64Kb Bytewide 5V F-RAM Memory
Features
64Kbit Ferroelectric Nonvolatile RAM
Organized as 8,192 x 8 bits
High Endurance 1 Trillion (1012) Read/Writes
38 year Data Retention (@ +75°C)
NoDelay™ Writes
Advanced High-Reliability Ferroelectric Process
Superior to BBSRAM Modules
No Battery Concerns
Monolithic Reliability
True Surface Mount Solution, No Rework Steps
Superior for Moisture, Shock, and Vibration
Resistant to Negative Voltage Undershoots
SRAM & EEPROM Compatible
JEDEC 8Kx8 SRAM & EEPROM pinout
70 ns Access Time
130 ns Cycle Time
Low Power Operation
15 mA Active Current
25 µA (typ.) Standby Current
Industry Standard Configuration
Industrial Temperature -40°C to +85°C
28-pin “Green”/RoHS SOIC Package
Description
The FM1608B is a 64-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or F-RAM is
nonvolatile but operates in other respects as a RAM.
It provides data retention for 38 years while
eliminating the reliability concerns, functional
disadvantages and system design complexities of
battery-backed SRAM (BBSRAM). Fast write timing
and high write endurance make F-RAM superior to
other types of nonvolatile memory.
In-system operation of the FM1608B is very similar
to other RAM devices. Minimum read- and write-
cycle times are equal. The F-RAM memory, however,
is nonvolatile due to its unique ferroelectric memory
process. Unlike BBSRAM, the FM1608B is a truly
monolithic nonvolatile memory. It provides the same
functional benefits of a fast write without the
disadvantages associated with modules and batteries
or hybrid memory solutions.
These capabilities make the FM1608B ideal for
nonvolatile memory applications requiring frequent
or rapid writes in a bytewide environment. The
availability of a true surface-mount package improves
the manufacturability of new designs. Device
specifications are guaranteed over an industrial
temperature range of -40°C to +85°C.
Pin Configuration
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VDD
27 WE
26 NC
25 A8
24 A9
23 A11
22 OE
21 A10
20 CE
19 DQ7
18 DQ6
17 DQ5
16 DQ4
15 DQ3
Ordering Information
FM1608B-SG
28-pin “Green”/RoHS SOIC
This is a product that has fixed target specifications but are subject
to change pending characterization results.
Rev. 1.2
Mar. 2011
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
http://www.ramtron.com
Page 1 of 11
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FM1608B pdf, 반도체, 판매, 대치품
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Precharge Operation
The precharge operation is an internal condition that
prepares the memory for a new access. All memory
cycles consist of a memory access and a precharge.
The precharge is initiated by deasserting the /CE pin
high. It must remain high for at least the minimum
precharge time tPC.
The user determines the beginning of this operation
since a precharge will not begin until /CE rises.
However, the device has a maximum /CE low time
specification that must be satisfied.
Endurance
Internally, a F-RAM operates with a read and restore
mechanism. Therefore, each read and write cycle
involves a change of state. The memory architecture
is based on an array of rows and columns. Each read
or write access causes an endurance cycle for an
entire row. In the FM1608B, a row is 64 bits wide.
Every 8-byte boundary marks the beginning of a new
row. Endurance can be optimized by ensuring
frequently accessed data is located in different rows.
Regardless, F-RAM offers substantially higher write
endurance than other nonvolatile memories. The
rated endurance limit of 1012 cycles will allow 3,000
FM1608B – 64Kb Bytewide 5V F-RAM
accesses per second to the same row for over 10
years.
F-RAM Design Considerations
When designing with F-RAM for the first time, users
of SRAM will recognize a few minor differences.
First, bytewide F-RAM memories latch each address
on the falling edge of chip enable. This allows the
address bus to change after starting the memory
access. Since every access latches the memory
address on the falling edge of /CE, users cannot
ground it as they might with SRAM.
Users who are modifying existing designs to use F-
RAM should examine the memory controller for
timing compatibility of address and control pins.
Each memory access must be qualified with a low
transition of /CE. In many cases, this is the only
change required. An example of the signal
relationships is shown in Figure 2 below. Also shown
is a common SRAM signal relationship that will not
work for the FM1608B.
The reason for /CE to strobe for each address is two-
fold: it latches the new address and creates the
necessary precharge period while /CE is high.
FRAM
Signaling
CE
Address
Data
Valid Strobing of /CE
A1
D1
A2
D2
SRAM
Signaling
CE
Address
Invalid Strobing of /CE
A1 A2
Data
D1 D2
Figure 2. Chip Enable and Memory Address Relationships
Rev. 1.2
Mar. 2011
Page 4 of 11
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FM1608B 전자부품, 판매, 대치품
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FM1608B – 64Kb Bytewide 5V F-RAM
Read Cycle AC Parameters (TA = -40° C to + 85° C, VDD = 4.5V to 5.5V unless otherwise specified)
Symbol Parameter
Min Max Units
tCE Chip Enable Access Time (to data valid)
tCA Chip Enable Active Time
tRC Read Cycle Time
tPC Precharge Time
tAS Address Setup Time
tAH Address Hold Time
tOE Output Enable Access Time
tHZ Chip Enable to Output High-Z
tOHZ Output Enable to Output High-Z
70 ns
70 ns
130 ns
60 ns
0 ns
15 ns
12 ns
15 ns
15 ns
Notes
1
1
Write Cycle AC Parameters (TA = -40° C to + 85° C, VDD = 4.5V to 5.5V unless otherwise specified)
Symbol Parameter
Min Max Units Notes
tCA Chip Enable Active Time
70 ns
tCW Chip Enable to Write High
70 ns
tWC Write Cycle Time
130 ns
tPC Precharge Time
60 ns
tAS Address Setup Time
0 ns
tAH Address Hold Time
15 ns
tWP Write Enable Pulse Width
40 ns
tDS Data Setup
30 ns
tDH Data Hold
0 ns
tWZ Write Enable Low to Output High Z
15 ns 1
tWX Write Enable High to Output Driven
10 ns 1
tHZ Chip Enable to Output High-Z
15 ns 1
tWS Write Enable Setup
0 ns 2
tWH Write Enable Hold
0 ns 2
Notes
1 This parameter is periodically sampled and not 100% tested.
2 The relationship between /CE and /WE determines if a /CE- or /WE-controlled write occurs. There is no timing
specification associated with this relationship.
Data Retention
Symbol Parameter
TDR @ +85ºC
@ +80ºC
@ +75ºC
Min
Max
Units
Notes
10 - Years
19 - Years
38 - Years
Rev. 1.2
Mar. 2011
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