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FM24C16B 데이터시트 PDF




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부품번호 FM24C16B 기능
기능 16Kb Serial 5V F-RAM Memory
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FM24C16B 데이터시트, 핀배열, 회로
www.DataSheet.co.kr
Preliminary
FM24C16B
16Kb Serial 5V F-RAM Memory
Features
16K bit Ferroelectric Nonvolatile RAM
Organized as 2,048 x 8 bits
High Endurance (1012) Read/Write Cycles
38 year Data Retention
NoDelay™ Writes
Advanced High-Reliability Ferroelectric Process
Fast Two-wire Serial Interface
Up to 1MHz maximum bus frequency
Direct hardware replacement for EEPROM
Supports legacy timing for 100 kHz & 400 kHz
Low Power Operation
5V operation
100 A Active Current (100 kHz)
4 A (typ.) Standby Current
Industry Standard Configuration
Industrial Temperature -40C to +85C
8-pin “Green”/RoHS SOIC (-G)
Description
The FM24C16B is a 16-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or FRAM is
nonvolatile and performs reads and writes like a
RAM. It provides reliable data retention for 38 years
while eliminating the complexities, overhead, and
system level reliability problems caused by EEPROM
and other nonvolatile memories.
The FM24C16B performs write operations at bus
speed. No write delays are incurred. Data is written to
the memory array in the cycle after it has been
successfully transferred to the device. The next bus
cycle may commence immediately without the need
for data polling. The FM24C16B is capable of
supporting 1012 read/write cycles, or a million times
more write cycles than EEPROM.
These capabilities make the FM24C16B ideal for
nonvolatile memory applications requiring frequent
or rapid writes. Examples range from data collection
where the number of write cycles may be critical, to
demanding industrial controls where the long write
time of EEPROM can cause data loss. The
combination of features allows the system to write
data more frequently, with less system overhead.
The FM24C16B provides substantial benefits to users
of serial EEPROM, and these benefits are available as
a hardware drop-in replacement. The FM24C16B is
available in an industry standard 8-pin SOIC package
and uses a familiar two-wire protocol. The
specifications are guaranteed over the industrial
temperature range from -40°C to +85°C.
Pin Configuration
NC
NC
NC
VSS
1
2
3
4
8 VDD
7 WP
6 SCL
5 SDA
Pin Names
SDA
SCL
WP
VSS
VDD
Function
Serial Data/Address
Serial Clock
Write Protect
Ground
Supply Voltage
Ordering Information
FM24C16B-G
“Green”/RoHS 8-pin SOIC
FM24C16B-GTR “Green”/RoHS 8-pin SOIC,
Tape & Reel
This is a product that has fixed target specifications but are subject
to change pending characterization results.
Rev. 1.3
July 2011
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
www.ramtron.com
Page 1 of 12
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FM24C16B pdf, 반도체, 판매, 대치품
www.DataSheet.co.kr
FM24C16B - 16Kb 5V I2C F-RAM
SCL
SDA
76
0
Stop
Start
(Master) (Master)
Data bits
(Transmitter)
Data bit Acknowledge
(Transmitter) (Receiver)
Figure 3. Data Transfer Protocol
Stop Condition
A stop condition is indicated when the bus master
drives SDA from low to high while the SCL signal is
high. All operations using the FM24C16B must end
with a Stop condition. If an operation is pending
when a Stop is asserted, the operation will be aborted.
The master must have control of SDA (not a memory
read) in order to assert a Stop condition.
Start Condition
A Start condition is indicated when the bus master
drives SDA from high to low while the SCL signal is
high. All read and write transactions begin with a
Start condition. An operation in progress can be
aborted by asserting a Start condition at any time.
Aborting an operation using the Start condition will
prepare the FM24C16B for a new operation.
If during operation the power supply drops below the
specified VDD minimum, the system should issue a
Start condition prior to performing another operation.
Data/Address Transfer
All data transfers (including addresses) take place
while the SCL signal is high. Except under the two
conditions described above, the SDA signal should
not change while SCL is high. For system design
considerations, keeping SCL in a low state while idle
improves robustness.
Acknowledge
The Acknowledge takes place after the 8th data bit has
been transferred in any transaction. During this state,
the transmitter should release the SDA bus to allow
the receiver to drive it. The receiver drives the SDA
signal low to acknowledge receipt of the byte. If the
receiver does not drive SDA low, the condition is a
No-Acknowledge and the operation is aborted.
The receiver would fail to acknowledge for two
distinct reasons. First is that a byte transfer fails. In
this case, the No-Acknowledge ends the current
operation so that the part can be addressed again.
This allows the last byte to be recovered in the event
of a communication error.
Second and most common, the receiver does not
acknowledge to deliberately end an operation. For
example, during a read operation, the FM24C16B
will continue to place data onto the bus as long as the
receiver sends Acknowledges (and clocks). When a
read operation is complete and no more data is
needed, the receiver must not acknowledge the last
byte. If the receiver acknowledges the last byte, this
will cause the FM24C16B to attempt to drive the bus
on the next clock while the master is sending a new
command such as a Stop.
Slave Address
The first byte that the FM24C16B expects after a
Start condition is the slave address. As shown in
Figure 4, the slave address contains the device type,
the page of memory to be accessed, and a bit that
specifies if the transaction is a read or a write.
Bits 7-4 are the device type and should be set to
1010b for the FM24C16B. The device type allows
other types of functions to reside on the 2-wire bus
within an identical address range. Bits 3-1 are the
page select. They specify the 256-byte block of
memory that is targeted for the current operation. Bit
0 is the read/write bit. A 0 indicates a write operation.
Rev. 1.3
July 2011
Page 4 of 12
Datasheet pdf - http://www.DataSheet4U.net/

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FM24C16B 전자부품, 판매, 대치품
www.DataSheet.co.kr
Ramtron
FM24C16B - 16Kb 5V I2C F-RAM
By Master
Start
Address
No
Acknowledge
S Slave Address 1 A
Data Byte
1P
By FM24C16B
Acknowledge
Data
Figure 7. Current Address Read
Stop
By Master
Start
Address
Acknowledge
No
Acknowledge
S Slave Address 1 A
Data Byte
A
Data Byte
1P
By FM24C16B
Acknowledge
Data
Figure 8. Sequential Read
Stop
By Master Start
Address
Start
Address
S Slave Address 0 A Word Address A S Slave Address 1 A
By FM24C16B
Acknowledge
Acknowledge
No
Acknowledge
Stop
Data Byte A Data Byte 1 P
Data
Figure 9. Selective (Random) Read
Endurance
The FM24C16B internally operates with a read and
restore mechanism. Therefore, endurance cycles are
applied for each read or write cycle. The memory
architecture is based on an array of rows and
columns. Each read or write access causes an
endurance cycle for an entire row. In the FM24C16B,
a row is 64 bits wide. Every 8-byte boundary marks
the beginning of a new row. Endurance can be
optimized by ensuring frequently accessed data is
located in different rows. Regardless, FRAM read
and write endurance is effectively unlimited at the
1MHz two-wire speed. Even at 3000 accesses per
second to the same row, 10 years time will elapse
before 1 trillion endurance cycles occur.
19 July 2011
7/12
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