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PDF FM25040B Data sheet ( Hoja de datos )
| Número de pieza | FM25040B | |
| Descripción | 4Kb Serial 5V F-RAM Memory | |
| Fabricantes | Ramtron | |
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Preliminary
FM25040B
4Kb Serial 5V F-RAM Memory
Features
4K bit Ferroelectric Nonvolatile RAM
• Organized as 512 x 8 bits
• High Endurance 1 Trillion (1012) Read/Writes
• 38 year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
Very Fast Serial Peripheral Interface - SPI
• Up to 20 MHz maximum Bus Frequency
• Direct hardware replacement for EEPROM
• SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1)
Description
The FM25040B is a 4-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or F-RAM is
nonvolatile but operates in other respects as a RAM.
It provides reliable data retention for 38 years while
eliminating the complexities, overhead, and system
level reliability problems caused by EEPROM and
other nonvolatile memories.
The FM25040B performs write operations at bus
speed. No write delays are incurred. Data is written to
the memory array immediately after it has been
successfully transferred to the device. The next bus
cycle may commence immediately without the need
for data polling. The FM25040B is capable of
supporting up to 1012 read/write cycles, or a million
times more write cycles than EEPROM.
These capabilities make the FM25040B ideal for
nonvolatile memory applications requiring frequent
or rapid writes. Examples range from data collection,
where the number of write cycles may be critical, to
demanding industrial controls where the long write
time of EEPROM can cause data loss.
The FM25040B provides substantial benefits to users
of serial EEPROM, in a hardware drop-in
replacement. The FM25040B uses the high-speed
SPI bus, which enhances the high-speed write
capability of F-RAM technology. The specifications
are guaranteed over an industrial temperature range
of -40°C to +85°C.
Sophisticated Write Protection Scheme
• Hardware Protection
• Software Protection
Low Power Consumption
• 250 µA Active Current (1 MHz)
• 4 µA (typ.) Standby Current
Industry Standard Configuration
• Industrial Temperature -40° C to +85° C
• 8-pin “Green”/RoHS SOIC (-G)
Pin Configuration
CS
SO
WP
VSS
1
2
3
4
8 VDD
7 HOLD
6 SCK
5 SI
Pin Names
/CS
/WP
/HOLD
SCK
SI
SO
VDD
VSS
Function
Chip Select
Write Protect
Hold
Serial Clock
Serial Data Input
Serial Data Output
Supply Voltage 5V
Ground
Ordering Information
FM25040B-G
“Green” 8-pin SOIC
FM25040B-GTR “Green” 8-pin SOIC,
Tape & Reel
This is a product that has fixed target specifications but are subject
to change pending characterization results.
Rev. 1.2
Feb. 2011
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-F-RAM, (719) 481-7000
www.ramtron.com
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FM25040B - 4Kb 5V SPI F-RAM
Data Transfer
All data transfers to and from the FM25040B occur
in 8-bit groups. They are synchronized to the clock
signal (SCK) and they transfer most significant bit
(MSB) first. The serial input data is clocked in on
the rising edge of SCK. The serial data output is
driven from the falling edge of SCK.
Command Structure
There are six commands called op-codes that can be
issued by the bus master to the FM25040B. They are
listed in the table below. These op-codes control the
functions performed by the memory. They can be
divided into three categories. First, there are
commands that have no subsequent data transfer.
They perform a single function, such as, enabling a
write operation. Second are commands followed by
one byte, either in or out. They operate on the status
register. Third are commands for memory
transactions followed by address and one or more
bytes of data.
Table 1. Op-code Commands
Name Description
WREN Set Write Enable Latch
WRDI Write Disable
RDSR Read Status Register
WRSR Write Status Register
READ Read Memory Data
WRITE Write Memory Data
Op-code
0000_0110b
0000_0100b
0000_0101b
0000_0001b
0000_A011b
0000_A010b
WREN - Set Write Enable Latch
The FM25040B will power up with writes disabled.
The WREN command must be issued prior to any
write operation. Sending the WREN op-code will
allow the user to issue subsequent op-codes for
write operations. These include writing the status
register and writing the memory.
Sending the WREN op-code causes the internal
Write Enable Latch to be set. A flag bit in the status
register, called WEL, indicates the state of the latch.
WEL=1 indicates that writes are permitted. A write
to the status register has no effect on the WEL bit.
Completing any write operation will automatically
clear the write-enable latch and prevent further
writes without another WREN command. Figure 5
below illustrates the WREN command bus
configuration.
WRDI - Write Disable
The WRDI command disables all write activity by
clearing the Write Enable Latch. The user can verify
that writes are disabled by reading the WEL bit in
the status register and verifying that WEL=0. Figure
6 illustrates the WRDI command bus configuration.
Figure 5. WREN Bus Configuration
Rev. 1.2
Feb. 2011
Figure 6. WRDI Bus Configuration
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Serial Data Bus Timing
CS
SCK
SI
SO
tCSU
1/tCK
tH
tSU
tF
tODV
tR
tOH
FM25040B - 4Kb 5V SPI F-RAM
tCL tCH
tD
tCSH
tOD
/Hold Timing
CS
SCK
HOLD
SO
Power Cycle Timing
tHS
tHH
tHS
tHH
tHZ
tLZ
Power Cycle Timing (TA = -40° C to + 85° C, VDD = 4.5V to 5.5V unless otherwise specified)
Symbol
Parameter
Min Max Units
tPU VDD(min) to First Access Start
tPD Last Access Complete to VDD(min)
tVR VDD Rise Time
tVF VDD Fall Time
10 - ms
0 - µs
30 - µs/V
100 - µs/V
Notes
1. Slope measured at any point on VDD waveform.
Notes
1
1
Rev. 1.2
Feb. 2011
Page 11 of 13
Datasheet pdf - http://www.DataSheet4U.net/
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet FM25040B.PDF ] | |
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