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PDF NL128102BM29-05A Data sheet ( Hoja de datos )

Número de pieza NL128102BM29-05A
Descripción Display Module
Fabricantes NEC 
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TFT MONOCHROME LCD MODULE
NL128102BM29-05A
48cm (19.0 Type)
SXGA
LVDS interface (2port)
DATA SHEET
DOD-PD-1193 (1st edition)
This DATA SHEET is updated document from
PRELIMINARY DATA SHEET DOD-PD-1064(5).
All information is subject to change without notice.
Please confirm the sales representative before
starting to design your system.
Document Number: DOD-PD-1193 (1st edition)
Published date: October 2005 CP(N)
1 © NEC LCD Technologies, Ltd.
2005 All rights reserved.
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NL128102BM29-05A
2. GENERAL SPECIFICATIONS
Display area
376.32 (H) × 301.056 (V) mm
Diagonal size of display 48cm (19.0 inches)
Drive system
Display grayscale
Pixel
a-Si TFT active matrix
256 gray scales per 1 sub-pixel (8-bit)
(766 gray scales per 1 pixel)
1,280 (H) × 1,024 (V) pixels (1 pixel consists of 3 sub-pixels (LCR).)
Pixel arrangement
LCR vertical stripe
Dot pitch
0.098 (H) × 0.294 (V) mm
Pixel pitch
0.294 (H) × 0.294 (V) mm
Module size
404.2 (W) × 330.0 (H) × 22.0 (D) mm (typ.)
Weight
2,900g (typ.)
Contrast ratio
Viewing angle
Designed viewing
direction
Polarizer surface
900:1 (typ.)
At the contrast ratio 10:1
Horizontal: Right side 85° (typ.), Left side 85° (typ.)
Vertical: Up side 85° (typ.), Down side 85° (typ.)
Viewing angle with optimum grayscale (γ= DICOM): normal axis (perpendicular)
Note1
Antiglare
Polarizer pencil-hardness
Response time
Luminance
Signal system
Power supply voltage
2H (min.) [by JIS K5400]
Ton+Toff (10%←→ 90%)
35ms (typ.)
At IBL=6.0mArms / lamp
1,000cd/m2 (typ.)
LVDS 2 port
[LCR 8-bit data signals, Dot clock (CLK), Data enable (DE)]
LCD panel signal processing board: 5.0V
Backlight
Edge light type: 6 cold cathode fluorescent lamps (without inverter)
Power consumption
At IBL=6.0mArms / lamp, Checkered flag pattern
26.8W (typ., Power dissipation of the inverter is not included.)
Note1: When the product luminance is 500cd/m2, the gamma characteristic is designed to γ=DICOM.
DATA SHEET DOD-PD-1193 (1st edition)
5
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4.4 POWER SUPPLY VOLTAGE SEQUENCE
VDD
Note1
0V
ON
4.5V
0.1ms < Tr < 80ms
NL128102BM29-05A
OFF
4.0V 4.5V
20ms max.
ON
Toff > 200ms
Display signals*
TxSEL signal
Note2
0V
10ms < t < 35ms
10ms < t < 35ms
VALID period
10ms < t < 35ms
10ms < t < 35ms
* These signals should be measured at the terminal of 100resistance.
Note1: In terms of voltage variation (voltage drop) while VDD rising edge is below 4.5V, a
protection circuit may work, and then this product may not work.
Note2: Display signals (DA0+/-, DA1+/-, DA2+/-, DA3+/-, CKA+/-, DB0+/-, DB1+/-, DB2+/-,
DB3+/-, CKB+/-) and TxSEL signal must be "0" voltage, exclude the VALID period (See
above sequence diagram). If these signals are higher than 0.3V, the internal circuit is
damaged.
If some of display and function signals of this product are cut while this product is working,
even if the signal input to it once again, it might not work normally. VCC should be cut when
the display and function signals are stopped.
Note3: The backlight should be turned on within the valid period of display and function signals, in
order to avoid unstable data display.
DATA SHEET DOD-PD-1193 (1st edition)
11
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