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PDF NL160120AM27-13A Data sheet ( Hoja de datos )
| Número de pieza | NL160120AM27-13A | |
| Descripción | Display Module | |
| Fabricantes | NEC | |
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TFT MONOCHROME LCD MODULE
NL160120AM27-13A
54 cm (21.3 Type)
UXGA
LVDS Interface (2 ports)
PRELIMINARY DATA SHEET
DOD-PD-1308 (1st edition)
All information is subject to change without notice.
Please confirm the sales representative before
starting to design your system.
Document Number: DOD-PD-1308 (1st edition)
Published date: January 2006 CP(N)
1 © NEC LCD Technologies, Ltd.
2006 All rights reserved.
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NL160120AM27-13A
2. GENERAL SPECIFICATIONS
Display area
432.0 (H) × 324.0 (V) mm
Diagonal size of display
Drive system
Display grayscale
Pixel
54 cm (21.3 inches)
a-Si TFT active matrix
256 gray scales per 1 sub-pixel (8-bit)
(766 gray scales per 1 pixel)
1,600 (H) × 1,200 (V) pixels (1 pixel consists of 3 sub-pixels (LCR).)
Pixel arrangement
Dot pitch
Pixel pitch
Module size
Weight
LCR vertical stripe
0.090 (H) × 0.270 (V) mm
0.270 (H) × 0.270 (V) mm
457.0 (W) × 350.0 (H) × 34.0 (D) mm (typ.)
2,900 g (typ.)
Contrast ratio
900:1 (typ.)
Viewing angle
At the contrast ratio ≥ 10:1
• Horizontal: Right side 85° (typ.), Left side 85° (typ.)
• Vertical: Up side 85° (typ.), Down side 85° (typ.)
Designed viewing direction
Viewing angle with optimum grayscale (γ= DICOM): normal axis (perpendicular)
Note1
Polarizer surface
Antiglare
Polarizer pencil-hardness 2H (min.) [by JIS K5400]
Response time
Ton+Toff (10%←→ 90%)
45 ms (typ.)
Luminance
At the maximum luminance control
1,800 cd/m2 (typ.)
Signal system
2 ports LVDS interface (THC63LVD824 THine Electronics, Inc. or equivalent)
[LCR 8-bit signals, Data enable signal (DE), Dot clock (CLK)]
Power supply voltage
Backlight
LCD panel signal processing board: 12.0V
Inverter: 12.0V
Direct light type: 16 cold cathode fluorescent lamps with an inverter
Replaceable part
• Inverter: 213PW041
Power consumption
At checkered flag pattern, the maximum luminance control
63.7 W (typ.)
Note1: When the product luminance is 500cd/m2, the gamma characteristic is designed to γ=DICOM.
PRELIMINARY DATA SHEET DOD-PD-1308 (1st edition)
5
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NL160120AM27-13A
4.4 POWER SUPPLY VOLTAGE SEQUENCE
4.4.1 LCD panel signal processing board
VDD
Note1
10.8V
0V
LVDS signals *1,*2
Note2
0V
CS, SDATI, SCLK
Note2
0V
ON
0.1ms < Tr < 80ms
OFF
9.6V 10.8V
VDD dip < 20ms
VALID period
t ≥ 20ms Note3
VALID period
ON
10.8V
Toff > 200ms
10ms < t < 35ms
10ms < t < 35ms
0ms < t < 35ms
*1: DA0+/-, DA1+/-, DA2+/-, DA3+/-, CKA+/-, DB0+/-, DB1+/-, DB2+/-, DB3+/- and CKB+/-
*2: LVDS signals should be measured at the terminal of 100Ω resistance.
Note1: In terms of voltage variation (voltage drop) while VDD rising edge is below 10.8V, a protection
circuit may work, and then this product may not work.
Note2: LVDS signals and CS, SDATI, SCLK must be Low or High-impedance, exclude the VALID
period (See above sequence diagram), in order to avoid that internal circuits is damaged.
If some of signals are cut while this product is working, even if the signal input to it once again,
it might not work normally. VDD should be cut when the display and function signals are
stopped.
Note3: At the beginning of the serial communication mode, take 20ms or more after the LVDS signal
input. As writing and reading the LUT data, see “4.11 TEN-bit LOOK UP TABLE FOR
GAMMA ADJUSTMENT”.
4.4.2 Inverter
Voltage
12.0V
11.4V
0V
tr≤800ms
0ms<t
BRTC
VDDB
Time
0ms<t
Note1: The backlight should be turned on within the valid period of LVDS signals, in order to avoid
unstable data display.
Note2: If tr is more than 800ms, the backlight will be turned off by a protection circuit for inverter.
Note3: When VDDB is 0V or BRTC is Low, PWSEL must be set to Low or Open.
PRELIMINARY DATA SHEET DOD-PD-1308 (1st edition)
11
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