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부품번호 BU99901GUZ-W
기능 WL-CSP EEPROM family
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BU99901GUZ-W 데이터시트, 핀배열, 회로
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High Reliability Serial EEPROMs
WL-CSP EEPROM family
I2C BUS
BU99901GUZ-W
Description
BU99901GUZ-W series is a serial EEPROM of I2C BUS interface method.
Features
1) Completely conforming to the world standard I2C BUS.
All controls available by 2 ports of serial clock (SCL) and serial data (SDA)
2) Other devices than EEPROM can be connected to the same port, saving microcontroller port.
3) 1.73.6V single power source action most suitable for battery use.
4) FAST MODE 400kHz at 1.73.6V
5) Page write mode useful for initial value write at factory shipment.
6) Auto erase and auto end function at data rewrite.
7) Low current consumption
At write operation (3.3V)
: 0.6mA (Typ.)
At read operation (3.6V)
: 0.6mA (Typ.)
At standby operation (3.6V) : 0.1µA (Typ.)
8) Write mistake prevention function
Write (write protect) function added
Write mistake prevention function at low voltage
9) Compact package
10) Data rewrite up to 100,000 times
11) Data kept for 40 years
12) Noise filter built in SCL / SDA terminal
13) Shipment data all address FFh
Page write
Product number
Number of pages
BU99901GUZ-W
32Byte
Absolute maximum ratings (Ta=25)
Parameter
symbol
Ratings
Impressed voltage
Permissible dissipation
VCC -0.3+6.5
Pd 220 *1
Storage temperature range
Tstg
-65+125
Action temperature range
Terminal voltage
Topr
-40+85
-0.3Vcc+1.0 *2
*1 When using at Ta=25or higher, 2.2mW to be reduced per 1
*2 The Max value of Terminal Voltage is not over 6.5V.
Unit
V
mW
V
Memory cell characteristics (Ta=25, Vcc=1.73.6V)
Parameter
Limits
Min. Typ.
Number of data rewrite times *1 1,000,000
Data hold years *1
40
*1 Not 100% TESTED
Max.
Recommended operating conditions
Parameter
Power source voltage
Write
Read
Input voltage
Symbol
Vcc
VIN
Ratings
2.73.3
1.73.6
0Vcc
Unit
Times
Years
Unit
V
V
No.10001EAT15
www.rohm.com
© 2010 ROHM Co., Ltd. All rights reserved.
1/16
2010.09 - Rev.A
Datasheet pdf - http://www.DataSheet4U.net/




BU99901GUZ-W pdf, 반도체, 판매, 대치품
www.DataSheet.co.kr
BU99901GUZ-W
Pin assignment and function
Technical Note
B B1 B2
B3
TEST GND
VDD
A A1 A2
A3
SDA SCL
WP
12
3
Fig.3 BU99901GUZ-W(bottom view)
Land No.
B3
B2
B1
A3
A2
A1
Terminal name
VDD
GND
TEST
WP
SCL
SDA
Input / output
Unit
Power Supply
Reference voltage of all input / output
Input
TEST terminal, Connect GND
Input
Write protect terminal
Input
Serial clock input
Input /output Slave and word address, Serial data input serial data output
Characteristic data (The following values are Typ. ones.)
6
5
Ta=-40℃
Ta=25℃
4 Ta=85℃
3 SPEC
2
1
0
0123456
Vcc(V)
Fig.4 'H' input voltage VIH1,2 (SCL,SDA,WP)
1
0.8
0.6 Ta=-40℃
Ta=25℃
Ta=85℃
0.4
SPEC
0.2
0
0123456
IOL2(mA)
Fig.7 'L' output voltage VOL-IOL(Vcc=2.5V)
6
5 Ta=-40℃
Ta=25℃
4 Ta=85℃
3
2
1
SPEC
0
0123456
Vcc(V)
Fig.5 'L' input voltage VIL (SCL,SDA,WP)
1.2
SPEC
1
0.8
0.6
Ta=-40℃
0.4 Ta=25℃
Ta=85℃
0.2
0
0123456
Vcc(V)
Fig.8 Input leak current ILI (SCL,WP)
1
Ta=-40℃
0.8 Ta=25℃
Ta=85℃
0.6
0.4
SPEC
0.2
0
0123456
IOL1(mA)
Fig.6 'L' output voltage VOL-IOL(Vcc=1.7V)
1.2
SPEC
1
0.8
0.6
0.4 Ta=-40℃
Ta=25℃
0.2 Ta=85℃
0
0123456
Vcc(V)
Fig.9 Output leak current
www.rohm.com
© 2010 ROHM Co., Ltd. All rights reserved.
4/16
2010.09 - Rev.A
Datasheet pdf - http://www.DataSheet4U.net/

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BU99901GUZ-W 전자부품, 판매, 대치품
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BU99901GUZ-W
Technical Note
I2C BUS communication
I2C BUS data communication
I2C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long,
and acknowledge is always required after each byte.
I2C BUS carries out data transmission with plural devices connected by 2 communication lines of serial data (SDA) and
serial clock (SCL).
Among devices, there are “master” that generates clock and control communication start and end, and “slave” that is
controlled by addresses peculiar to devices.
EEPROM becomes “slave”. And the device that outputs data to bus during data communication is called “transmitter”,
and the device that receives data is called “receiver”.
SDA
1-7 8 9
1-7 8 9
1-7 8
SCL
S
START ADDRESS
condition
R/W ACK
DATA
ACK
Fig.34 Data transfer timing
DATA
9
P
ACK STOP
condition
Start condition (start bit recognition)
Before executing each command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when SCL
is 'HIGH' is necessary.
This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this condition is
satisfied, any command is executed.
Stop condition (stop bit recognition)
Each command can be ended by SDA rising from 'LOW' to 'HIGH' when stop condition (stop bit), namely, SCL is 'HIGH'
Acknowledge (ACK) signal
This acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In
master and slave, the device (µ-COM at slave address input of write command, read command, and this IC at data
output of read command) at the transmitter (sending) side releases the bus after output of 8bit data.
The device (this IC at slave address input of write command, read command, and µ-COM at data output of read
command) at the receiver (receiving) side sets SDA 'LOW' during 9 clock cycles, and outputs acknowledge signal (ACK
signal) showing that it has received the 8bit data.
This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) 'LOW'.
Each write action outputs acknowledge signal) (ACK signal) 'LOW', at receiving 8bit data (word address and write data).
Each read action outputs 8bit data (read data), and detects acknowledge signal (ACK signal) 'LOW'.
When acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (µ-COM) side, this
IC continues data output. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, and
recognizes stop condition (stop bit), and ends read action. And this IC gets in standby status.
Device addressing
Output slave address after start condition from master.
The significant 4 bits of slave address are used for recognizing a device type.
The device code of this IC is fixed to '1010'.
The most insignificant bit ( R / W --- READ / WRITE ) of slave address is used for designating write or read action, and is
as shown below.
Setting R / W to 0 --- write (setting 0 to word address setting of random read)
Setting R / W to 1 --- read
Type
BU99901GUZ-W
Slave address
1 1 1 0 0 0 0 R/W
www.rohm.com
© 2010 ROHM Co., Ltd. All rights reserved.
7/16
2010.09 - Rev.A
Datasheet pdf - http://www.DataSheet4U.net/

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WL-CSP EEPROM family

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